A Low-Spur Fractional-N DPLL With Analog Pre-Distortion DTC Implementing Second-/Third-Order Calibration https://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg 150 150 https://secure.gravatar.com/avatar/8fcdccb598784519a6037b6f80b02dee03caa773fc8d223c13bfce179d70f915?s=96&d=mm&r=g
Abstract:
This article presents a low-spur, low-jitter fractional-N digital phase-locked loop (DPLL) employing an analog pre-distortion digital-to-time converter (APD-DTC) to suppress fractional spurs by compensating for both second- and third-order nonlinearities without using complex digital pre-distortion. To support background calibration, a spur-level detection scheme using phase detector gain (PDG) is proposed …