Neural networks

  • No Comments

PANDA: A Reconfigurable Seizure Prediction and Detection Neural Network Accelerator for Epilepsy Monitoring

PANDA: A Reconfigurable Seizure Prediction and Detection Neural Network Accelerator for Epilepsy Monitoring 150 150
Author(s): Siyuan Qiu, Xiaoyi Song, Xiangjie Song, Changchun Zhou, Xiaoyan Song, Jie Yang, Wenjin Wang, Yuchao Yang, Hailong Jiao

Abstract:

For effective healthcare management of epilepsy patients in a non-hospital environment, continuous monitoring of EEG signals is crucial, where wearable intelligent devices are essential. The existing seizure monitoring devices, however, cannot achieve high sensitivity, a short detection latency, a low false alarm rate (FAR), as well as ultra-low-power computing simultaneously. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3699609
Publisher: IEEE

View on IEEE Xplore

  • No Comments

MixCIM: A Hybrid Computing-in-Memory Macro With Less Data-Movement and Better Memory-Reuse for Depthwise Separable Neural Networks

MixCIM: A Hybrid Computing-in-Memory Macro With Less Data-Movement and Better Memory-Reuse for Depthwise Separable Neural Networks 150 150
Author(s): Xin Qiao, Youming Yang, Jiahao Song, Renjie Wei, Xiyuan Tang, Meng Li, Runsheng Wang, Yuan Wang

Abstract:

Computing-in-memory (CIM) architectures have demonstrated strong potential for edge artificial intelligence (AI) devices due to their enhanced parallelism and energy efficiency. With the growing complexity of AI tasks and the rapid increase in model size, computation and deployment costs have surged. Depthwise separable neural networks (DSNNs) have attracted interest for …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3651775
Publisher: IEEE

View on IEEE Xplore

  • No Comments

SparseCol: A 1320 BTOPS/W Precision-Scalable NPU Exploiting Training-Free Structured Bit-Level Sparsity and Dynamic Dataflow

SparseCol: A 1320 BTOPS/W Precision-Scalable NPU Exploiting Training-Free Structured Bit-Level Sparsity and Dynamic Dataflow 150 150
Author(s): Man Shi, Vikram Jain, Weijie Jiang, Chao Fang, Antony Joseph, Wim Dehaene, Marian Verhelst

Abstract:

Bit-serial computation enables sequential processing of data at the bit level, providing several advantages, such as scalable computational precision. This approach has gained significant attention, especially for exploiting bit-level sparsity (BLS) in AI workloads. While current bit-serial processors leverage BLS to eliminate the computation associated with zero bits, they face …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3636451
Publisher: IEEE

View on IEEE Xplore

Search this website