Multiplexing

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A Synchronized Phase-Shifted Time-Multiplexed Uplink Wireless Power and Data Transfer System for Implantable Voltammetry

A Synchronized Phase-Shifted Time-Multiplexed Uplink Wireless Power and Data Transfer System for Implantable Voltammetry 150 150
Author(s): Zhenhao Li, Junyao Tang, Nawab Singh, Jianqiang Jiang, Lei Zhao, Wenshuo Zhu, Xuan Sun, Liang Dong, Cheng Huang

Abstract:

Existing single-link wireless power and data transfer (WPDT) systems for implantable biosensors support either closed-loop power regulation or sensor data uplink, but not both simultaneously, resulting in degraded efficiency and restricted sensing. This work presents a 13.56-MHz WPDT system with: 1) a synchronized phase-shifted time-multiplexed uplink scheme enabling TX power regulation …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3730406
Publisher: IEEE

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A 92.1-dB SNDR Easy-Driving Two-Step NS-SAR-Based Incremental ADC With Concurrent Gain-Error Plus Noise Suppression

A 92.1-dB SNDR Easy-Driving Two-Step NS-SAR-Based Incremental ADC With Concurrent Gain-Error Plus Noise Suppression 150 150
Author(s): Chenyang Li, Tzu-Han Wang, Dongsuk Kang, Ken Li, Xitie Zhang, Wei-En Lee, Visvesh S. Sathe, Shaolan Li

Abstract:

This article presents a two-step incremental analog-to-digital converter (ADC) that achieves high resolution and energy efficiency while substantially easing the input driving constraints and interstage gain variation. By employing a level-shifted sub-ranging architecture with an input-tracking (IT) feature, the design obviates direct input sampling, thereby significantly relaxing the demands on …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 884 – 897
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3635146
Publisher: IEEE

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Side-Channel Attack-Resistant HMAC-SHA256 Accelerator With Boolean and Arithmetic Masking in Intel 4 CMOS

Side-Channel Attack-Resistant HMAC-SHA256 Accelerator With Boolean and Arithmetic Masking in Intel 4 CMOS 150 150
Author(s): Sachin Taneja, Vikram B. Suresh, Raghavan Kumar, Vivek De, Sanu K. Mathew

Abstract:

This work describes a side-channel attack (SCA)-resistant hash-based message authentication code (HMAC) accelerator with secure hash algorithm 2 (SHA-2) using Boolean and arithmetic masking along with the first-reported ASIC implementation in Intel 4 CMOS with 10 M measured traces. Previously reported masked datapath suffers from high area/performance overheads (>100%) designs due to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1026 – 1036
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3647096
Publisher: IEEE

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