A CMOS Probabilistic Computing Chip with Hardware-Aware Learning https://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg 150 150 https://secure.gravatar.com/avatar/8fcdccb598784519a6037b6f80b02dee03caa773fc8d223c13bfce179d70f915?s=96&d=mm&r=g
Abstract:
This work demonstrates a compact probabilistic computing system based on a physics-inspired p-bit architecture with 440 interacting spins configured in a Chimera graph and occupying 0.44 mm² of silicon area. Area efficiency is achieved through a current-mode neuron update circuit and a mixed-signal design approach that integrates pitch-matched standard-cell analog blocks with …