Metals

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A 37.8 Mb/mm² SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection

A 37.8 Mb/mm² SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection 150 150
Author(s): Harold Pilo, Manish Arora, Chien-An Lai, Mike Lee, Zack Lo, Mayur Randeria

Abstract:

A high-density (HD), SRAM-based register file (RF) has been demonstrated in Intel 18A Technology (Wang et al., 2025 and Pilo et al., 2025) featuring RibbonFET GAA transistors and a back side power delivery network (BSDPN). The RF is optimized for HD and array efficiency and achieves a density of 37.8 Mb/mm2, the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 357 – 360
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3628176
Publisher: IEEE

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Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node

Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node 150 150
Author(s): Piyush Kumar, Da Eun Shim, Azad Naeemi

Abstract:

This work presents a comprehensive spin-orbit torque (SOT)-based magnetic random access memory (MRAM) design at the 7 nm technology node, spanning from device-level characteristics to system-level power performance area (PPA). At the device level, we show the tradeoffs among the write current, error rate, and time, based on mircomagnetic simulations. …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 139 – 147
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3621279
Publisher: IEEE

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Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard-Cell Scaling

Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard-Cell Scaling 150 150
Author(s): Anup Ashok Kedilaya, Sirish Oruganti, Nishant Gupta, Xiuhao Zhang, Ilya Karpov, Mark A. Anders, Jaydeep P. Kulkarni

Abstract:

Advances in process technology enabling backside metals (BSMs) and contacts offer new design–technology co-optimization (DTCO) opportunities to further enhance power, performance, and area gains (PPA) in sub-3-nm nodes. This work exploits backside (BS) contact technology within standard cells to extend both signal and clock routing to BSM layers, …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 107 – 115
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3617784
Publisher: IEEE

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3-D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency

3-D Stacked HBM and Compute Accelerators for LLM: Optimizing Thermal Management and Power Delivery Efficiency 150 150
Author(s): Janak Sharda, Madison Manley, Jungyoun Kwak, Chinsung Park, Muhannad Bakir, Shimeng Yu

Abstract:

Advanced packaging is becoming essential for designing hardware accelerators for large language models (LLMs). Different architectures, such as 2.5-D integration of memory with logic, have been proposed; however, the bandwidth limits the throughput of the complete system. Recent works have proposed memory on logic systems, where high bandwidth memory (HBM) …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 116 – 122
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3617298
Publisher: IEEE

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Two 7–13-GHz GaAs-SiGe Four–Channel Beamforming Chiplets With/Without Metallic Interlayer Shields

Two 7–13-GHz GaAs-SiGe Four–Channel Beamforming Chiplets With/Without Metallic Interlayer Shields 150 150
Author(s): Nengxu Zhu, Yiting Zhang, Genyin Ma, Fanyi Meng

Abstract:

This letter presents two 7–13-GHz GaAs-SiGe four-channel beamforming chiplets to minimize the chip area. The chips integrate GaAs-based power amplifiers (PAs) and low-noise amplifiers (LNAs) with silicon-based phase and amplitude control modules using gold bumps. To mitigate coupling between the metal patterns of the heterogeneous chips and avoid interference with …

Published in: IEEE Solid-State Circuits Letters
Page(s): 161 – 164
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3573757
Publisher: IEEE

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