Memory

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A Practical MRAM Logic-in-Memory Platform With Reference-Bitline Structure

A Practical MRAM Logic-in-Memory Platform With Reference-Bitline Structure 150 150
Author(s): Seongmin Ahn, Minjun Jang, Mingu Han, Bayartulga Ishdorj, Siyeol Lee, Taehui Na

Abstract:

The memory wall due to data movement is a major challenge that limits performance and energy efficiency in bitwise-operation-intensive applications. To address this issue, this article proposes a global merged reference-based magnetic random access memory (MRAM) logic-in-memory (LIM) structure. The proposed structure generates operation-specific reference resistances by controlling the effective …

Published in: IEEE Solid-State Circuits Letters
Page(s): 266 – 269
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3729230
Publisher: IEEE

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Algorithm–Architecture Co-Design for Vertically Integrated AI and HPC Systems: Challenges, Advantages, and Future Outlook

Algorithm–Architecture Co-Design for Vertically Integrated AI and HPC Systems: Challenges, Advantages, and Future Outlook 150 150
Author(s): Patricia Gonzalez-Guerrero, Aaron R. Young, Giuseppe Di Guglielmo, Benjamin Parpillon, Narasinga Rao Miniskar, Nikhil Kumar Cherukuri, Abhay Nayak, Meriam Gay Bautista-Jurney, Mario Vega, George Michelogiannakis, Thom Popovici, Yu Cao, Jeffrey S. Vetter, John Shalf, Farah Fahim

Abstract:

Next-generation scientific instruments in high-energy physics, X-ray imaging, fusion diagnostics, and other data-intensive applications generate data rates that increasingly exceed practical communication bandwidth and power budgets, making the traditional approach of transferring raw data to remote computing systems unsustainable. This paper presents the Vertically Integrated AI for Sensing and High-Performance …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3742652
Publisher: IEEE

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Device–Circuit–System Co-Design of Reconfigurable Oxide–Semiconductor 2T Nonvolatile Gain-Cell Memory and Sandwich-3-D LLM Accelerator

Device–Circuit–System Co-Design of Reconfigurable Oxide–Semiconductor 2T Nonvolatile Gain-Cell Memory and Sandwich-3-D LLM Accelerator 150 150
Author(s): Luqi Zheng, Chang Niu, Shuting Du, Sumi Lee, Amir Massah Bavani, Zehao Lin, Peide D. Ye, Haitong Li

Abstract:

In this work, we present an oxide–semiconductor (OS)-based 2T nonvolatile gain-cell (NVGC) memory and a “sandwich 3-D” stacking scheme, co-designed using atomic layer deposition (ALD) InOx oxide–semiconductor FETs (OSFETs) and OS-ferroelectric FETs (FeFETs), for efficient large language model (LLM) acceleration. The new 2T-NVGC enables native, in-memory reconfiguration …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 240 – 248
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740041
Publisher: IEEE

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Nanoelectromechanically Gated Gain Cell eDRAM

Nanoelectromechanically Gated Gain Cell eDRAM 150 150
Author(s): Collin P. Finnan, Choong-Ho Rhee, Tahir Ghani, Tsu-Jae King-Liu

Abstract:

The memory wall and the slowdown of static random access memory (SRAM) scaling have renewed interest in gain-cell embedded dynamic random access memory (DRAM). While gain cells offer high density and energy efficiency, they suffer from limited retention, parasitic coupling, and the need for boosted write voltages. This work introduces …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 223 – 230
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3717204
Publisher: IEEE

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DTCO of NOR-Type IGZO FeFETs for 3-D Heterogeneous AI Memories: A Read-Centric Perspective

DTCO of NOR-Type IGZO FeFETs for 3-D Heterogeneous AI Memories: A Read-Centric Perspective 150 150
Author(s): Yang Xiang, Zhuo Chen, Nicolò Ronchi, Arvind Sharma, Fernando García-Redondo, Subhali Subhechha, Attilio Belmonte, Maarten Rosmeulen, Gouri Sankar Kar, Dwaipayan Biswas, Jan Van Houdt

Abstract:

InGaZnO (IGZO)-channel FeFETs have attracted notable interest thanks to recent advances in endurance, opening up their application space for read-dominated AI memory tiers. This work evaluates the viability of NOR-type IGZO FeFETs for 3-D heterogeneous AI memories from a read-centric design-technology co-optimization (DTCO) perspective, spanning on-chip back-end-of-line (BEOL) random-access …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 249 – 255
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740054
Publisher: IEEE

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A Current-Mode Nondestructive Circuit Readout Scheme for High-Density 3-D Ferroelectric Memory

A Current-Mode Nondestructive Circuit Readout Scheme for High-Density 3-D Ferroelectric Memory 150 150
Author(s): Chaohan Wang, Wagdy Hussein, Yang Xiang, Shankha Mukherjee, Ismail Cevik, Fernando García-Redondo, Annachiara Spagnolo, Hyungrock Oh, Marie Garcia Bardon, Nick van Helleputte, Julien Ryckaert, Geert Hellings, Dwaipayan Biswas, Jan van Houdt

Abstract:

The AI era is demanding ever-increasing memory capacity and bandwidth, where 3-D-stacked ferroelectric memory (FeRAM) utilizing nondestructive readout (NDRO) ferroelectric capacitors (FeCAPs) stand as a promising candidate. This work addresses NDRO sensing signal challenges in deeply scaled 3-D FeRAMs using a current-mode sensing scheme, co-designed with the device architecture to …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 199 – 204
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3727137
Publisher: IEEE

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Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile 1-bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference

Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile 1-bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference 150 150
Author(s): Byeong-Gwon Kim, Byeong-Kwon Ju, Ki-Young Lee

Abstract:

The spin-transfer-torque magnetic random access memory (STT-MRAM) is attractive for nonvolatile 1-bit sign-weight storage, but a favorable cell or local-read metric does not establish subsystem efficiency. We analyze a hybrid magnetic tunnel junction (MTJ)–complementary metal–oxide–semiconductor (CMOS) memory subsystem, in which MTJs store static signs while sensing, reference …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 192 – 198
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3726699
Publisher: IEEE

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HEMAIA: A 16 nm Heterogeneous Multi-Accelerator SoC With Accelerator-Centric Execution

HEMAIA: A 16 nm Heterogeneous Multi-Accelerator SoC With Accelerator-Centric Execution 150 150
Author(s): Ryan Antonio, Xiaoling Yi, Jun Yin, Ce Ma, Yunhao Deng, Fanchen Kong, Abdelrahman Ayman Fathallah, Joren Dumoulin, Josse van Delm, Tiago Knorst, Adrian Kneip, Guilherme Paim, Wim Dehaene, Marian Verhelst

Abstract:

Emerging heterogeneous AI workloads span classic computer vision, modern transformers, and complex neuro-symbolic (NeSy) pipelines. These workloads demand multi-accelerator SoCs that integrate uniquely designed engines and orchestrate them efficiently. Two systemic bottlenecks arise from existing heterogeneous SoCs: 1) mismatched accelerator data access patterns, spanning bandwidth, dataflow, and data layout, reduce effective …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 19
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3739314
Publisher: IEEE

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A Hybrid-Bonded 12.1 TOPS/mm2 56-Core DNN Processor With 2.5 Tb/s/mm2 3D Network on Chip in Intel 18A and Intel 3

A Hybrid-Bonded 12.1 TOPS/mm2 56-Core DNN Processor With 2.5 Tb/s/mm2 3D Network on Chip in Intel 18A and Intel 3 150 150
Author(s): Phil C. Knag, Gregory K. Chen, Shanshan Xie, Satish Yada, Wei Wu, Yu-Shiang Lin, Alexander Kashirin, Xiemei Meng, Russell Criss, Ana Sonia Leon, Carlos Tokunaga, Ram K. Krishnamurthy, James W. Tschanz

Abstract:

This article presents a modular 3D stacked manycore processor that integrates a general-purpose RISC-V base die with a domain-specific deep neural network (DNN) accelerator die using a 9 $\mu $ m hybrid-bonded interconnect (HBI). A custom $14 \times 4~\times 2$ 3D network-on-chip (3D NoC) provides a flat, distributed shared-memory address space across 112 tiles, enabling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3735250
Publisher: IEEE

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