Memory

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Open DRAM Model Part II: Enabling Processing-in-Memory in 3D DRAM

Open DRAM Model Part II: Enabling Processing-in-Memory in 3D DRAM 150 150
Author(s): Kiseok Lee, Seongkwang Lim, Suman Datta, Shimeng Yu

Abstract:

Processing-in-memory (PIM) by implementing Boolean logic function in DRAM has been proposed to alleviate the memory wall problem in data-intensive computing. However, quantitatively evaluating DRAM-based logic operations across different DRAM architectures remains challenging due to the lack of publicly available DRAM cell and peripheral transistor models that accurately capture their …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704508
Publisher: IEEE

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A 1.87-TELOPS/W 3-D Ising Machine for Accelerated Quantum Monte Carlo With Reconfigurability Using CMOS p-Bits

A 1.87-TELOPS/W 3-D Ising Machine for Accelerated Quantum Monte Carlo With Reconfigurability Using CMOS p-Bits 150 150
Author(s): Ming-Che Li, Archisman Ghosh, Risi Kumar Jaiswal, Supriyo Datta, Shreyas Sen

Abstract:

Qubit-based quantum annealing processors operate at ultra-low temperatures (15 mK) requiring enormous cooling energy. Consequently, there is a lot of interest in quantum Monte Carlo (QMC) algorithms that can be used to emulate quantum computing on classical machines. However, prior classical emulators implemented on CPUs, GPUs, or field-programmable gate arrays (FPGAs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3699984
Publisher: IEEE

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A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2

A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2 150 150
Author(s): Marco Pasotti, Riccardo Zurla, J. J. Bertolini Agnoletto, Emanuela Calvetti, Alessio Antolini, Andrea Lico, Giuseppe Desoli, Riccardo Vignali, Luca Iannelli, Luigi Croce, Francesco Zavalloni, Eleonora Franchi Scarselli, Alessandro Cabrini

Abstract:

In-memory computing (IMC) hardware accelerators for deep neural networks (DNNs) require storing a massive number of coefficients within a single computing macro to avoid performance degradation in multicore clusters. This aspect, often overlooked by common figures of merit (FoMs), can be effectively addressed by phase-change memory (PCM) technology, thanks to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3693894
Publisher: IEEE

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A 11.0-TOPS/W Diffusion Accelerator With Temporal Data Reuse for Real-Time Text-to-Motion Generation

A 11.0-TOPS/W Diffusion Accelerator With Temporal Data Reuse for Real-Time Text-to-Motion Generation 150 150
Author(s): Sungwoong Yune, Jieon Yoon, Hangyeol Lee, Adiwena Putra, Jaehoon Heo, Joo-Young Kim

Abstract:

Text-to-motion models are AI systems that generate human motion sequences directly from natural language descriptions, serving as key enablers for immersive virtual avatars and interactive digital humans in AR/VR ecosystems. However, state-of-the-art text-to-motion diffusion models suffer from substantial computational costs due to their iterative nature, making them ill-suited for …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3689546
Publisher: IEEE

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QVGA CMOS LiDAR Sensor With nMOS-Only SPAD Analog Front-End and Area-Efficient Priority Histogramming TDC

QVGA CMOS LiDAR Sensor With nMOS-Only SPAD Analog Front-End and Area-Efficient Priority Histogramming TDC 150 150
Author(s): Minkyung Kim, Hyeongseok Seo, Songhyeon Kim, Jung-Hoon Chun, Seong-Jin Kim, Jaehyuk Choi

Abstract:

This article presents a high-resolution (HR) CMOS light detection and ranging (LiDAR) sensor capable of generating quarter video graphics array (QVGA) ( $320~{\times }~240$ ) depth images. To support high pixel density, the sensor employs a compact 6-transistor (6-T) nMOS-only single-photon avalanche diode (SPAD) analog front-end (AFE) with a column-shared active recharge circuit. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3687569
Publisher: IEEE

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