Machine Learning

Birch: A Real-Time Multi-Domain Multi-Task Extended Reality Perception Accelerator

Birch: A Real-Time Multi-Domain Multi-Task Extended Reality Perception Accelerator 150 150

Abstract:

Birch is a system-on-chip (SoC) that efficiently and accurately accelerates the multi-task multi-domain extended reality (XR) perception pipeline, with workloads such as visual inertial odometry (VIO), eye gaze tracking, and scene understanding. Birch features vision modules with cascaded line buffers, in-step feature sorting, and double-buffered optical flow to extract and …

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A 7.5-μW 35-Keyword End-to-End Keyword Spotting System With Random Augmented On-Chip Training

A 7.5-μW 35-Keyword End-to-End Keyword Spotting System With Random Augmented On-Chip Training 150 150

Abstract:

Fully integrated keyword spotting (KWS) systems designed for low-power operation face two major challenges. First, increasing the number of supported keywords significantly raises system complexity and power consumption. Second, most existing systems are not personalized to individual users, as they are trained on data from native English speakers, leading to …

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HUTAO: A Reconfigurable Homomorphic Processing UniT With Cache-Aware Operation Scheduling

HUTAO: A Reconfigurable Homomorphic Processing UniT With Cache-Aware Operation Scheduling 150 150

Abstract:

Fully homomorphic encryption (FHE) enables privacy-preserving machine learning (PPML) at the cost of intensive computational overhead, which necessitates the use of domain-specific accelerators. To achieve comprehensive support for leveled FHE, this article presents a reconfigurable multi-scheme FHE processor that supports both client-side encryption/decryption and server-side evaluation. First, a reconfigurable …

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A 65-nm CMOS Machine-Learning-Enhanced Bandwidth-Efficient LiDAR

A 65-nm CMOS Machine-Learning-Enhanced Bandwidth-Efficient LiDAR 150 150

Abstract:

We present a proof-of-concept light detection and ranging (LiDAR) signal processing architecture that integrates a machine-learning-enhanced processing unit (PU) with on-chip time-to-digital converters (TDCs) to reduce bandwidth and memory requirements in SPAD-based direct time-of-flight (dToF) systems. The proposed architecture fits a Gaussian mixture model (GMM) to photon arrival time distributions …

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A Machine Learning-Inspired PAM-4 Transceiver for Medium-Reach Wireline Links

A Machine Learning-Inspired PAM-4 Transceiver for Medium-Reach Wireline Links 150 150

Abstract:

This article presents an energy-efficient machine learning-inspired PAM-4 wireline transceiver that leverages data encoding at the transmitter (Tx) and feature extraction with classification at the receiver (Rx) to compensate for channel loss ranging from 13 to 26 dB, while maintaining the bit error rate (BER)<10-11. A new consecutive symbol-to-center (CSC) encoding …

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