A Low-Power MRAM-Based Nonvolatile Flip-Flop Architecture for Register and System Applications https://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg 150 150 https://secure.gravatar.com/avatar/8fcdccb598784519a6037b6f80b02dee03caa773fc8d223c13bfce179d70f915?s=96&d=mm&r=g
Abstract:
This work presents a minimal nonvolatile flip-flop (NVFF) hybrid architecture and an NV static contention-free differential FF (nvSCDFF) cell that reduces the overhead associated with replicated NV circuitry in conventional in situ NVFFs while enabling low power. By using only one NVFF per column and compact SCDFF-based volatile flip-flops (FFs), …