A Sampling PLL with Boosted Phase Detection Gain Achieving 52 fs RMS Jitter and 110.4 MHz Lock-in Range https://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg 150 150 https://secure.gravatar.com/avatar/8fcdccb598784519a6037b6f80b02dee03caa773fc8d223c13bfce179d70f915?s=96&d=mm&r=g
Abstract:
This work presents a sampling PLL (SPLL) that simultaneously achieves sub-sampling PLL-level jitter and wide lock-in range (flock) inherent to SPLL architecture. By employing a high phase detection gain, the proposed SPLL ensures low in-band phase noise dominated by reference, while maintaining robust re-locking without auxiliary frequency-locked loop (FLL). Fabricated …