Inverters

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A High-Speed D-FF and a 11-Bit Up-Down Counter Using Unipolar Oxide TFTs on a Flexible Foil

A High-Speed D-FF and a 11-Bit Up-Down Counter Using Unipolar Oxide TFTs on a Flexible Foil 150 150
Author(s): Suyash Shrivastava, Pydi Ganga Bahubalindruni

Abstract:

This manuscript presents an experimental characterization of a novel high speed D flip-flop (D-FF). The circuit was fabricated on a 27μm thick flexible polyimide substrate using a NMOS only, single gate amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor technology (TFT). Reliable response of the D-FF was noticed from measurements up to a clock …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3636192
Publisher: IEEE

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Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET

Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET 150 150
Author(s): Swati Deshwal, Sufia Shahin, Anirban Kar, Yogesh S. Chauhan, Hussam Amrouch

Abstract:

This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature instability (NBTI), hot carrier degradation (HCD), and the impact of back-end-of-line (BEOL) parasitics on standard cell performance. NBTI degradation is modeled using a framework …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 188 – 196
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3624653
Publisher: IEEE

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A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core

A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core 150 150
Author(s): Berkay Özbek, Timothy G. Constandinou

Abstract:

This letter presents an adaptable ring oscillator (RO)-true random number generator (TRNG) that removes the fixed power–throughput tradeoff by selecting delay-cell physics at run time. A hybrid core uses a current-starved inverter in low-power (LP) mode to amplify slew-limited jitter for high bit-efficiency at low frequency, and a …

Published in: IEEE Solid-State Circuits Letters
Page(s): 325 – 328
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3621413
Publisher: IEEE

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Non-Volatile ReRAM-Based Compact Event-Triggered Counters

Non-Volatile ReRAM-Based Compact Event-Triggered Counters 150 150
Author(s): Moin Diwan, Shengchao Zhang, Zidu Li, Alex James, Bhaskar Choubey

Abstract:

With an increasing number of transistors per circuit, the fabrication cost and the energy consumption of each integrated circuits increase exponentially, which drives the need to reduce the number of transistors. In this study, we explore a novel design for a 16-bit digital counter that utilizes a combination of complementary …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 131 – 138
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3619415
Publisher: IEEE

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Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS

Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS 150 150
Author(s): Anojh Kumaran Rajendra, Harijot Singh Bindra, Bram Nauta

Abstract:

This article introduces two comparators featuring a dynamic-bias preamplifier and self-clocked latches, tailored for ultra-low-power and medium-speed applications with <500- $\mu $ V input-referred noise (IRN). The proposed self-clocked latches are activated by the preamplifier outputs and therefore operate with a lower common-mode current, which in turn minimizes the crowbar current …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3612157
Publisher: IEEE

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High-Entropy Analog-Based Strong Physical Unclonable Function With Area-to-Entropy-ratio of 166 F2/bit

High-Entropy Analog-Based Strong Physical Unclonable Function With Area-to-Entropy-ratio of 166 F2/bit 150 150
Author(s): Alessandro Catania, Sebastiano Strangio, Maksym Paliy, Christian Sbrana, Michele Bertozzi, Giuseppe Iannaccone

Abstract:

In this letter, we present a high-entropy strong physically unclonable function (PUF) utilizing weak-inversion current mirrors implemented in a standard 65-nm CMOS technology. Each response bit of the proposed PUF relies on the threshold voltage differences of minimum-sized transistors arranged in a $32\times 32$ matrix. The analog operating principle enables encoding …

Published in: IEEE Solid-State Circuits Letters
Page(s): 309 – 312
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3616263
Publisher: IEEE

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Dual-Junction Monolithically Integrated Monitoring Photodiode With a Two-Stage 18 GHz 18 pA/√Hz TIA in 22-nm FDSOI

Dual-Junction Monolithically Integrated Monitoring Photodiode With a Two-Stage 18 GHz 18 pA/√Hz TIA in 22-nm FDSOI 150 150
Author(s): Jelle H. T. Bakker, Nimit Jain, Paul Klatser, Mark S. Oude Alink, Bram Nauta

Abstract:

We present a monolithically integrated (MI) dualjunction monitoring photodiode (PD) and transimpedance amplifier (TIA). The photocurrent originates from the deep Nwell (DNW)/P-type substrate (PSUB) $({\lt }5~ \mathrm {GHz})$ and the P-Well $(\mathrm {PW}) / \mathrm {DNW}({\gt }1~ \mathrm {GHz})$ junctions. The presented combination of bulk PD and 22 nm fully-depleted silicon-on-insulator (FDSOI) …

Published in: IEEE Solid-State Circuits Letters
Page(s): 313 – 316
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3615656
Publisher: IEEE

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Design and Verification of Low Parasitic MOS Capacitors With Series Connected Tri-Well Junctions

Design and Verification of Low Parasitic MOS Capacitors With Series Connected Tri-Well Junctions 150 150
Author(s): Zhendong Li, Yongjuan Shi, Yifan Jiang, Chen Hu, Junting Chen, Mengyuan Hua, Xun Liu, Junmin Jiang

Abstract:

This letter presents a tri-well implementation of MOS capacitors designed to tackle the challenge of high parasitic capacitance. By serially connecting the three parasitic well junction capacitors between the three wells (N-Well, deep P-Well, and deep N-Well) and substrate (PSUB), the parasitic capacitance can be significantly decreased. A higher bias …

Published in: IEEE Solid-State Circuits Letters
Page(s): 277 – 280
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3608282
Publisher: IEEE

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A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation

A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation 150 150
Author(s): Woojin Lee, Changmin Sim, Changjoo Kim, Jinwoo Jeon, Hyundo Jung, Taihyun Kim, Chulwoo Kim

Abstract:

This work presents a capacitive-latch (C-latch) true random number generator (TRNG) that achieves both inverter mismatch autozeroing and accelerated evaluation by utilizing coupling capacitors. The proposed C-latch TRNG samples the mismatch between inverter equalization voltages through coupling capacitors during the equalization phase, effectively autozeroing inverter mismatch and enabling high-entropy raw …

Published in: IEEE Solid-State Circuits Letters
Page(s): 265 – 268
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3608187
Publisher: IEEE

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