Inverters

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A 0.5–2.5-GS/s Resettable Ring-VCO-Based ADC Eliminating Quantization-Noise Shaping

A 0.5–2.5-GS/s Resettable Ring-VCO-Based ADC Eliminating Quantization-Noise Shaping 150 150
Author(s): Tao Lu, Zixiang Liu, Hao Yang, Sai-Weng Sin, Fujiang Lin, Liheng Lou, Robert Bogdan Staszewski, Yizhe Hu

Abstract:

This article presents a Nyquist-rate Analog-to-digital converter (ADC) operating from 0.5 to 2.5 GS/s based on an open-loop resettable ring VCO (R-RVCO). By inherently embedding the $1 {\,}-{\,}z^{-1}$ transfer function, the R-RVCO eliminates the need for an explicit differentiator, suppresses VCO phase-noise (PN) integration, and avoids quantization-noise (QN) shaping within …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3668599
Publisher: IEEE

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A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique

A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique 150 150
Author(s): Riccardo Moleri, Simone M. Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Abstract:

This work presents a digital-to-time converter (DTC)-based fractional-N digital phase-locked loop (PLL) designed to achieve simultaneously low jitter and low spurs. We introduce a novel DTC chopping technique that effectively mitigates fractional spurs, which we identify as predominantly arising from even-order nonlinearity invariable-slope (VS) DTCs. The proposed technique suppresses …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663074
Publisher: IEEE

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A 0.19-PEF Bandwidth/Power Scalable Dynamic Amplifier

A 0.19-PEF Bandwidth/Power Scalable Dynamic Amplifier 150 150
Author(s): Yihang Cheng, Yihan Zhang, Huaqiang Wu, Sining Pan

Abstract:

This letter presents an energy-efficient dynamic amplifier. It utilizes source-coupled input boosting and time-domain differential sampling techniques to boost the effective input signal by $4\times $ compared to its floating inverter amplifier (FIA) prototype without noise or power penalties. With discharge-based dynamic biasing, the bandwidth (BW) and power of the amplifier …

Published in: IEEE Solid-State Circuits Letters
Page(s): 93 – 96
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3668876
Publisher: IEEE

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A 94-fs Jitter and −249.3-dB FoM MDLL With Background Calibration of Injection Phase and Slew-Rate Mismatch

A 94-fs Jitter and −249.3-dB FoM MDLL With Background Calibration of Injection Phase and Slew-Rate Mismatch 150 150
Author(s): Dongjun Park, Jae-Yoon Sim, Seon-Kyoo Lee

Abstract:

This article presents a ring oscillator (RO)-based multiplying delay-locked loop (MDLL) that incorporates a dual-background calibration scheme to compensate for both injection phase and slew-rate mismatches. The MDLL employs the proposed frequency/slew-rate detector (FSD) to distinguish both mismatch types by comparing the pulse widths of consecutive output clock …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3648361
Publisher: IEEE

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A Standalone-in-Memory Voltage Crossover-Based Assist Switching Circuit for Reliable and Efficient Process Tracking Memory Vmin Improvement in Intel 18A-RibbonFET Technology

A Standalone-in-Memory Voltage Crossover-Based Assist Switching Circuit for Reliable and Efficient Process Tracking Memory Vmin Improvement in Intel 18A-RibbonFET Technology 150 150
Author(s): Saroj Satapathy, Amlan Ghosh, John Riley, Jalal Quadri, Jaydeep Kulkarni, Feroze Merchant

Abstract:

Advanced CMOS memory requires voltage biasing assist techniques to achieve low operating voltages (Vmin), which must be deactivated at higher voltages for high electric field reliability. Centralized power management unit (PMU) control signals face timing synchronization and process tracking challenges when distributed across cores to activate assist circuits in various …

Published in: IEEE Solid-State Circuits Letters
Page(s): 37 – 40
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3652110
Publisher: IEEE

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A High-Speed D-FF and a 11-Bit Up-Down Counter Using Unipolar Oxide TFTs on a Flexible Foil

A High-Speed D-FF and a 11-Bit Up-Down Counter Using Unipolar Oxide TFTs on a Flexible Foil 150 150
Author(s): Suyash Shrivastava, Pydi Ganga Bahubalindruni

Abstract:

This manuscript presents an experimental characterization of a novel high speed D flip-flop (D-FF). The circuit was fabricated on a $27\mu $ m thick flexible polyimide substrate using a nMOS only, single gate amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) technology. Reliable response of the D-FF was noticed from measurements up to …

Published in: IEEE Solid-State Circuits Letters
Page(s): 373 – 376
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3636192
Publisher: IEEE

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Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET

Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET 150 150
Author(s): Swati Deshwal, Sufia Shahin, Anirban Kar, Yogesh S. Chauhan, Hussam Amrouch

Abstract:

This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature instability (NBTI), hot carrier degradation (HCD), and the impact of back-end-of-line (BEOL) parasitics on standard cell performance. NBTI degradation is modeled using a framework …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 188 – 196
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3624653
Publisher: IEEE

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A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core

A 168 nW to 44.3 Mb/s Adaptable TRNG With 400 mV Attack-Resilient Hybrid RO Core 150 150
Author(s): Berkay Özbek, Timothy G. Constandinou

Abstract:

This letter presents an adaptable ring oscillator (RO)-true random number generator (TRNG) that removes the fixed power–throughput tradeoff by selecting delay-cell physics at run time. A hybrid core uses a current-starved inverter in low-power (LP) mode to amplify slew-limited jitter for high bit-efficiency at low frequency, and a …

Published in: IEEE Solid-State Circuits Letters
Page(s): 325 – 328
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3621413
Publisher: IEEE

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Non-Volatile ReRAM-Based Compact Event-Triggered Counters

Non-Volatile ReRAM-Based Compact Event-Triggered Counters 150 150
Author(s): Moin Diwan, Shengchao Zhang, Zidu Li, Alex James, Bhaskar Choubey

Abstract:

With an increasing number of transistors per circuit, the fabrication cost and the energy consumption of each integrated circuits increase exponentially, which drives the need to reduce the number of transistors. In this study, we explore a novel design for a 16-bit digital counter that utilizes a combination of complementary …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 131 – 138
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3619415
Publisher: IEEE

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