Hysteresis

Analysis and Design of a 10.4-ENOB 0.92–5.38- $\mu$ W Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications

Analysis and Design of a 10.4-ENOB 0.92–5.38- $\mu$ W Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications 150 150

Abstract:

Level-crossing ADCs (LCADCs) operate on changes in the input signal, resulting in an event-driven power consumption and data output. For signals with time-sparse activity (e.g., neural action potentials, and ECG), such ADCs can offer advantages at the system level through the reduced data rate that decreases the transmission and/…

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