Frequency locked loops

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A Wide-Lock-in-Range and Fast-Settling-Time, 11.6-to-14-GHz SSPLL With an Event-Driven FLL and a Low-Power Harmonic-Lock Detector

A Wide-Lock-in-Range and Fast-Settling-Time, 11.6-to-14-GHz SSPLL With an Event-Driven FLL and a Low-Power Harmonic-Lock Detector 150 150
Author(s): Youngjun Kim, Siheon Lee, Taehyub Kim, Sunhaeng Heo, Younghyun Lim

Abstract:

This article presents a wide-lock-in-range and fast-settling-time, 11.6-to-14-GHz subsampling phase-locked loop (PLL) subsampling PLL (SSPLL) using an event-driven frequency-locked loop (ED-FLL) and a harmonic-lock detector (HLD). The ED-FLL becomes active only when a frequency disturbance, $f_{\mathrm {D}}$ , is detected, rapidly corrects the frequency error using a lock-expedition algorithm, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3729681
Publisher: IEEE

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A 16 MHz RC Frequency Reference With ±450 ppm Inaccuracy From –45 °C to 85 °C After Accelerated Aging

A 16 MHz RC Frequency Reference With ±450 ppm Inaccuracy From –45 °C to 85 °C After Accelerated Aging 150 150
Author(s): Karimeldeen Mohamed, Nandor G. Toth, Hui Jiang, Çağrı Gürleyük, Kofi A. A. Makinwa

Abstract:

This article presents a high-accuracy, low-drift 16MHz RC frequency reference implemented in a standard 180 nm CMOS process. It consists of a frequency-locked loop (FLL), which locks the output frequency of a digitally controlled oscillator (DCO) to the time constant of a Wien Bridge (WB) filter. A PNP-based temperature sensor (TS) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 9
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3673972
Publisher: IEEE

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A 60-GHz Low-Noise mmWave Divider-Less Fractional-N Cascaded PLL Achieving −250.2-dB FoMJ in 28-nm CMOS

A 60-GHz Low-Noise mmWave Divider-Less Fractional-N Cascaded PLL Achieving −250.2-dB FoMJ in 28-nm CMOS 150 150
Author(s): Jaehong Jung, Eunseok Lee, Donghyeon Han, Jinchen Wang, Anantha P. Chandrakasan, Ruonan Han

Abstract:

This article presents a fractional- ${ {N}}$ cascaded phase-locked loop (PLL) operating in the mmWave band from 55.8 to 64.2 GHz. The cascaded architecture consists of a first-stage fractional- ${ {N}}$ reference-sampling (RS) PLL and a second-stage sub-sampling (SS) PLL, incorporating two key innovations. The first-stage RS-PLL leverages a fully differential voltage-domain quantization-noise cancellation (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3652928
Publisher: IEEE

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An Aging-Robust 32-MHz RC Frequency Reference With 0.4-ppm Allan Deviation and ±1550-ppm Inaccuracy From −40 °C to 125 °C After a 1-Point Trim

An Aging-Robust 32-MHz RC Frequency Reference With 0.4-ppm Allan Deviation and ±1550-ppm Inaccuracy From −40 °C to 125 °C After a 1-Point Trim 150 150
Author(s): Sining Pan, Xiaohan Liu, Junlong Zeng, Yihang Cheng, Kofi. A. A. Makinwa, Huaqiang Wu

Abstract:

This letter presents an aging-robust 32-MHz RC frequency reference based on a frequency-locked-loop (FLL). With a temperature compensation scheme that combines BJTs and aging-robust diffusion resistors, the FLL achieves ±1550-ppm inaccuracy from $-40~^{\circ }$ C to $125~^{\circ }$ C after batch calibration and a low-cost 1-point trim, which increases to ±2350-ppm …

Published in: IEEE Solid-State Circuits Letters
Page(s): 81 – 84
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3664504
Publisher: IEEE

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A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations

A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations 150 150
Author(s): Sayan Kumar, Teerachot Siriburanon, Sumit Dash, Patchara Sawakewang, Shuja Andrabi, Jon Strange, Khurram Muhammad, Chih-Ming Hung, Robert Bogdan Staszewski

Abstract:

We propose a new ping-pong (PP) charge-sharing locking (CSL) phase-locked loop (PLL) architecture that enhances the strength of charge-injection into the oscillator’s LC-tank using complementary charge-sharing capacitors during both positive and negative halves of the reference clock, effectively achieving an implicit $2times $ reference frequency multiplication. The design includes a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1368 – 1383
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3535888
Publisher: IEEE

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