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A Low-Noise Fast-Switching Transconductor for Sub-Sampling PLLs

A Low-Noise Fast-Switching Transconductor for Sub-Sampling PLLs 150 150
Author(s): Abhishek Kumar, Nagendra Krishnapura

Abstract:

Sub-sampling PLLs use a transconductor following the sampling phase detector. To reduce the loop-filter capacitor size, a small transconductance with polarity switching can drive a switched-capacitor loop filter; however, slow settling introduces uncertainty in the PLL parameters, and excess output noise directly contributes to PLL jitter. Realizing a small transconductance …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3743715
Publisher: IEEE

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A 32-Gb/s/λ, 256-Gb/s/Fiber Half-Rate Bandpass-Filtered Clock-Forwarding DWDM Optical Link in a 3-D-Stacked 7-nm EIC/65-nm PIC Technology

A 32-Gb/s/λ, 256-Gb/s/Fiber Half-Rate Bandpass-Filtered Clock-Forwarding DWDM Optical Link in a 3-D-Stacked 7-nm EIC/65-nm PIC Technology 150 150
Author(s): Sanquan Song, Nikola Nedovic, Nandish Mehta, Angad S. Rekhi, Georgios Kalogerakis, Li Xu, Brian Zimmer, Stephen G. Tell, Yoshinori Nishi, Xi Chen, Ward Lopes, Benjamin G. Lee, Thomas H. Greer, C. Thomas Gray

Abstract:

We present a 32-Gb/s/ $\lambda $ dense wavelength-division multiplexing (DWDM) bandpass-filtered clock-forwarding link with nine channels on a 200-GHz grid: eight for data and one for clock forwarding, intended for next-generation co-packaged optics (CPO). Using an injection-locked oscillation (ILO) technique for jitter filtering, the forwarded clock (FWDCLK) tracks most of …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 18
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3733977
Publisher: IEEE

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A Low-Power 10Mbps Squaring-First UWB Receiver Using Frequency Hopping and Two-Tone Modulation

A Low-Power 10Mbps Squaring-First UWB Receiver Using Frequency Hopping and Two-Tone Modulation 150 150
Author(s): Lexie Drackley, Aman Gupta, David D. Wentzloff

Abstract:

This paper presents a low-power 10Mbps squaring-first ultra-wideband (UWB) receiver using frequency hopping code-division multiple-access (FH-CDMA) and two-tone OOK modulation for wireless personal area networks (WPAN). The two-tone receiver architecture preserves IF filtering, improves resilience to narrowband interference, and saves power by eliminating the RF local oscillator. FH is applied …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3716852
Publisher: IEEE

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Integrated Low-Power Self-Coherent Kramers–Kronig Millimeter-Wave Receiver With Nonlinear Analog and Mixed-Signal Computing

Integrated Low-Power Self-Coherent Kramers–Kronig Millimeter-Wave Receiver With Nonlinear Analog and Mixed-Signal Computing 150 150
Author(s): Sherif Ghozzy, Muhamed Allam, Emir Ali Karahan, Zheng Liu, Kaushik Sengupta

Abstract:

A critical challenge in scaling up high-frequency wireless communication in the millimeter-Wave (mmWave) spectrum has been poor energy efficiency of the constituent transceivers, particularly on the highly energy constrained user equipment (UE). Receiving spectrally-efficient wireless signals (e.g., 64-quadrature amplitude modulation (QAM) etc.) require coherent transceivers with programmable frequency synthesizers, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 18
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3720585
Publisher: IEEE

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A Calibration-Free Frequency-Scalable ΔΣ ADC Incorporating PVT-Robust Dynamic Integration

A Calibration-Free Frequency-Scalable ΔΣ ADC Incorporating PVT-Robust Dynamic Integration 150 150
Author(s): Tohru Kaneko, Hideaki Ishida, Yuzuru Yamaki, Satoshi Takehara, Un-Ku Moon

Abstract:

This article summarizes a calibration-free, frequency-scalable $Delta Sigma $ analog-to-digital converter (ADC) which employs dynamic open-loop integrators for low-power sensing systems. The integrators use a capacitive degeneration scheme to obtain an integration factor determined by a capacitor ratio. To enhance process-voltage-temperature (PVT) robustness, bottom-plate level shift (BPLS) and a timer are …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3719645
Publisher: IEEE

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A Tunable RF Self-Interference Canceller With Highly Accelerated, Machine-Learning-Based Adaptation for Full-Duplex Radio Applications

A Tunable RF Self-Interference Canceller With Highly Accelerated, Machine-Learning-Based Adaptation for Full-Duplex Radio Applications 150 150
Author(s): Xichen Li, Ahmed Refaat Aboulsaad, Elpida Karapepera, Yi-Hsiang Huang, Po-Hao Cheng, Charles Chien, Jacques Christophe Rudell

Abstract:

Future full-duplex (FD) radio systems require highly tunable self-interference (SI) cancellers with rapid adaptation to mitigate dynamic SI profiles in wireless environments. This article presents a 2.4-GHz RF SI canceller chip with extensive tuning capabilities that operates with a machine-learning (ML)-augmented adaptation loop for FD transceivers. The proposed design …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715631
Publisher: IEEE

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An Ultra-Low-Jitter Sampling-Filter-Based Charge-Pump PLL With Resistive-Discharge Time-Amplifying Phase-Frequency Detector and Series-Resonance VCO

An Ultra-Low-Jitter Sampling-Filter-Based Charge-Pump PLL With Resistive-Discharge Time-Amplifying Phase-Frequency Detector and Series-Resonance VCO 150 150
Author(s): Feng Bu, Depeng Sun, Dingtao Zeng, Yuan Gao, Bowen Wang, Zhicheng Dong, Xiaoteng Zhao, Hao Xu, Na Yan, Ruixue Ding, Shubin Liu, Zhangming Zhu

Abstract:

This article presents a 13-GHz quadrature charge-pump phase-locked loop (CPPLL) that simultaneously achieves ultra-low jitter and low-spur performance. First, a low-noise resistive-discharge time-amplifying phase-frequency detector (RD-TAPFD) is proposed, achieving extremely low inherent noise and significantly suppressing noise from the following stages. Second, a sampling-based dual-path loop filter effectively suppresses reference …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3690771
Publisher: IEEE

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A 256-Element Slepian Beamforming Accelerator With Analog Compute-In-Memory Multiplication and Accumulation

A 256-Element Slepian Beamforming Accelerator With Analog Compute-In-Memory Multiplication and Accumulation 150 150
Author(s): Wei-Chun Wang, Shida Zhang, Coleman DeLude, Laith Shamieh, Nael Mizanur Rahman, Isha Chakraborty, Justin Romberg, Saibal Mukhopadhyay

Abstract:

An analog compute-in-memory (CIM) Slepian beamforming (SBF) accelerator is introduced for large-scale multi-input–multi-output (MIMO). The design performs complex-valued vector–matrix multiplication in the analog domain to project 256 I/Q inputs into a low-dimensional Slepian subspace and uses a digital backend with 4-tap FIR filters to generate one output beam. …

Published in: IEEE Solid-State Circuits Letters
Page(s): 154 – 157
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3690381
Publisher: IEEE

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A 6.8–14-GHz Ring-Based Sampling-PLL Achieving 69.3-fs Jitter Under 50-mV Supply Noise

A 6.8–14-GHz Ring-Based Sampling-PLL Achieving 69.3-fs Jitter Under 50-mV Supply Noise 150 150
Author(s): Mahmoud A. Khalil, Mohamed Badr Younis, Ruhao Xia, Ahmed E. Abdelrahman, Tianyu Wang, Kyu-Sang Park, Pavan Kumar Hanumolu

Abstract:

This article presents a type-III wide-bandwidth ring-oscillator-based analog phase-locked loop (PLL) optimized for low-jitter performance in noisy supply environments. The design uses an 812.5-MHz reference frequency and a high-gain sampling phase detector to achieve a closed-loop bandwidth over 100 MHz, effectively reducing the intrinsic phase noise of the ring oscillator. To …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3683111
Publisher: IEEE

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