Field programmable gate arrays

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A CMOS Probabilistic Computing Chip With Hardware-Aware Learning

A CMOS Probabilistic Computing Chip With Hardware-Aware Learning 150 150
Author(s): Jinesh Jhonsa, William Whitehead, Yihao Wu, David Mccarthy, Shuvro Chowdhury, Kerem Y. Camsari, Luke Theogarajan

Abstract:

This work demonstrates a compact probabilistic computing system based on a physics-inspired probabilistic bit (p-bit) architecture with 440 interacting spins configured in a chimera graph and occupying 0.44 mm2 of silicon area. Area efficiency is achieved through a current-mode neuron update circuit and a mixed-signal design approach that integrates pitch-matched standard-cell analog …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 86 – 94
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3689506
Publisher: IEEE

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A 11.0-TOPS/W Diffusion Accelerator With Temporal Data Reuse for Real-Time Text-to-Motion Generation

A 11.0-TOPS/W Diffusion Accelerator With Temporal Data Reuse for Real-Time Text-to-Motion Generation 150 150
Author(s): Sungwoong Yune, Jieon Yoon, Hangyeol Lee, Adiwena Putra, Jaehoon Heo, Joo-Young Kim

Abstract:

Text-to-motion models are AI systems that generate human motion sequences directly from natural language descriptions, serving as key enablers for immersive virtual avatars and interactive digital humans in AR/VR ecosystems. However, state-of-the-art text-to-motion diffusion models suffer from substantial computational costs due to their iterative nature, making them ill-suited for …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3689546
Publisher: IEEE

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Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising–Similarity for Diffusion Models

Denim: Heterogeneous Compute-in-Memory Accelerator Exploiting Denoising–Similarity for Diffusion Models 150 150
Author(s): Ruiqi Guo, Lei Wang, Xiaofeng Chen, Keyi Jiang, Zhiheng Yue, Huiming Han, Yang Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin

Abstract:

Diffusion models have recently revolutionized the field of image synthesis due to their ability to generate photorealistic images. However, one of the main drawbacks of diffusion models is that the image generation process is expensive. Large image-to-image networks have to be applied multiple times in order to iteratively optimize the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3684745
Publisher: IEEE

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HyFPCiM: A 65-nm 417-μW Error-Sensitivity-Aware FP8 Compute-in-Memory Macro

HyFPCiM: A 65-nm 417-μW Error-Sensitivity-Aware FP8 Compute-in-Memory Macro 150 150
Author(s): Gaurav Kumar K, Yatharth Agarwal, Kaushik Roy

Abstract:

This letter presents HyFPCiM, a 65-nm FP8 compute-in-memory (CiM) macro that enables sub-mW floating-point (FP) inference using error-sensitivity-aware FP partitioning (EAP). EAP maps exponent processing to a digital CiM (DCiM) path and mantissa accumulation to an analog CiM (ACiM), avoiding the power- and area-intensive adder-tree-based accumulation used in prior FP-CiM …

Published in: IEEE Solid-State Circuits Letters
Page(s): 146 – 149
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3688988
Publisher: IEEE

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LUT-Based Convolutional Tsetlin Machine Accelerator With Dynamic Clause Scaling for Resources-Constrained FPGAs

LUT-Based Convolutional Tsetlin Machine Accelerator With Dynamic Clause Scaling for Resources-Constrained FPGAs 150 150
Author(s): Rashed Al Amin, Roman Obermaisser

Abstract:

The rapid growth of machine learning (ML) workloads, particularly in computer vision applications, has significantly increased computational and energy demands in modern electronic systems, motivating the use of hardware accelerators to offload processing from general-purpose processors. Despite advances in computationally efficient ML models, achieving energy-efficient inference on resource-constrained edge devices …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 45 – 55
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3676833
Publisher: IEEE

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A 27.5–28.5 mJ/Frame 3-D Gaussian Rendering Processor With Spherical Beta Illumination and Mixed-Precision Computation Path

A 27.5–28.5 mJ/Frame 3-D Gaussian Rendering Processor With Spherical Beta Illumination and Mixed-Precision Computation Path 150 150
Author(s): Cheng Nian, Xiaorui Mo, Jiaqi Zhang, Fasih Ud Din Farrukh, Jiaying Peng, Fei Chen, Chun Zhang

Abstract:

This letter presents a 3-D Gaussian rendering processor that integrates a spherical beta (SB) illumination module with a mixed-precision rendering engine to enable energy-efficient novel-view synthesis on edge devices. SB replaces spherical harmonics (SH) with a hardware-efficient kernel implemented using a pipelined fixed-point piecewise linear (PWL) power unit. The pipeline …

Published in: IEEE Solid-State Circuits Letters
Page(s): 113 – 116
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3676726
Publisher: IEEE

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On-Chip Charge-Trap-Transistor-Based Mismatch Calibration of an 8-Bit Thermometer Current-Source DAC

On-Chip Charge-Trap-Transistor-Based Mismatch Calibration of an 8-Bit Thermometer Current-Source DAC 150 150
Author(s): Mohammadreza Zeinali, Sudhakar Pamarti

Abstract:

This letter presents an on-chip mismatch calibration technique for current-source digital-to-analog converters (DACs) using charge-trap transistors (CTTs) in 22-nm FDSOI technology. The proposed method exploits programmable threshold voltage (VTH) shifts in CTTs to locally tune the current of near-minimum-sized devices without external trimming. A compact 8-bit thermometer DAC is implemented …

Published in: IEEE Solid-State Circuits Letters
Page(s): 53 – 56
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3656261
Publisher: IEEE

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A RISC-V SoC With Reconfigurable Custom Instructions on a Synthesized eFPGA Fabric in 22nm FinFET

A RISC-V SoC With Reconfigurable Custom Instructions on a Synthesized eFPGA Fabric in 22nm FinFET 150 150
Author(s): Prashanth Mohan, Siddharth Das, Ken Mai

Abstract:

This letter presents a flexible and energy-efficient RISC-V system-on-chip (SoC) in 22nm FinFET technology, achieving state-of-the-art performance by tightly integrating the CPU with a synthesized embedded FPGA (embedded field programmable gate array (eFPGA)), enabling the implementation of reconfigurable custom instructions. The tight integration of the eFPGA with SoC scratchpad memory …

Published in: IEEE Solid-State Circuits Letters
Page(s): 321 – 324
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3618942
Publisher: IEEE

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