Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model https://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg 150 150 https://secure.gravatar.com/avatar/8fcdccb598784519a6037b6f80b02dee03caa773fc8d223c13bfce179d70f915?s=96&d=mm&r=g
Abstract:
We present a framework for design technology co-optimization (DTCO) of the main memory system with one transistor-one capacitor (1T1C) ferroelectric random access memory (FERAM) as an alternative to dynamic random access memory (DRAM). We start with the ferroelectric capacitor device model and perform array-level memory circuit simulation. Then, we …