Eyes

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A 12-Gb/s Source-Synchronous Single-Ended PAM-4 Transceiver With Background Adaptive Crosstalk Equalization in 28-nm CMOS

A 12-Gb/s Source-Synchronous Single-Ended PAM-4 Transceiver With Background Adaptive Crosstalk Equalization in 28-nm CMOS 150 150
Author(s): DongArm Shin, Kuy Youn Chung, Sihoon Yang, SeongHwan Cho

Abstract:

This article presents a background adaptive crosstalk (XT) equalization technique for a single-endedfour-level pulse amplitude modulation (PAM-4) interface to maintain accurate XT cancellation (XTC) under environmental variations. A least-mean-square (LMS) adaptation loop adjusts the XT equalizer using a source-synchronous clock as an aggressor reference uncorrelated with the victim. At the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5409 – 5420
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3712021
Publisher: IEEE

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A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS

A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS 150 150
Author(s): Kshitiz Tyagi, Kunbo Ma, Joung Won Park, Behzad Razavi

Abstract:

We present a transceiver architecture for single-ended PAM4 signaling, introducing an inverter-based active-inductor-terminated front end that obviates the need for further equalizer stages, substantially reducing power and area. Realized in 28-nm CMOS technology, the four-lane link operates at 64 Gb/s/pin with a bit error rate (BER) less than $10{^{-12}}$ …

Published in: IEEE Solid-State Circuits Letters
Page(s): 230 – 233
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3721808
Publisher: IEEE

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A 40-Gb/s 8-mW-OMA GaN-Based 1-to-N VCSEL Driver for Parallel and Wireless Optical Transmitter Frontends

A 40-Gb/s 8-mW-OMA GaN-Based 1-to-N VCSEL Driver for Parallel and Wireless Optical Transmitter Frontends 150 150
Author(s): S. Sarah Feng, Fuzhan Chen, H. Bruce Bao, R. Matthew Ma, Kangping Zhong, P. T. Alan Lau, C. Patrick Yue

Abstract:

This letter presents a broadband, high-optical modulation amplitude (OMA) GaN-based 1-to-N VCSEL driver implemented in a 150-nm GaN HEMT process for parallel and wireless optical transmitter frontends. It further compares split-node and conventional VCSEL-driving topologies and analyzes the bandwidth scaling and inter-VCSEL timing skew of series- and parallel-connected VCSEL arrays. …

Published in: IEEE Solid-State Circuits Letters
Page(s): 242 – 245
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3720689
Publisher: IEEE

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An 11.5-Gb/s/pin, 0.4-V Driver-Supply Transmitter With Switched-Coupling Charge-Pump-Based Crosstalk Cancellation for Ultra-Dense Capacitively Coupled Channels

An 11.5-Gb/s/pin, 0.4-V Driver-Supply Transmitter With Switched-Coupling Charge-Pump-Based Crosstalk Cancellation for Ultra-Dense Capacitively Coupled Channels 150 150
Author(s): Yoochang Kim, Seunghoon Yi, Seung Chae Jung, Hee-Cheol Joo, Young-Ha Hwang

Abstract:

This work presents an 11.5-Gb/s/pin transmitter (TX) for ultra-dense capacitively coupled channels that achieves near-complete eye-margin recovery while operating from a 0.4-V driver supply using a switched-coupling charge-pump-based crosstalk cancellation (SCCP-XTC) scheme. In the proposed scheme, one of four precharged capacitor banks in each XT cancellation (XTC) path …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715082
Publisher: IEEE

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A 0.1514-pJ/bit 18-Gb/s/wire Run-Length-Tolerant Transition-Driven AC-Coupled Transceiver for Die-to-Die Interfaces

A 0.1514-pJ/bit 18-Gb/s/wire Run-Length-Tolerant Transition-Driven AC-Coupled Transceiver for Die-to-Die Interfaces 150 150
Author(s): Jun-Cheol Lee, Joo-Hyung Chae

Abstract:

This article presents a transition-driven AC-coupled transceiver (TRX) optimized for low-power and compact die-to-die (D2D) interfaces. To address the limitations of conventional PMOS- and transimpedance-amplifier (TIA)-based receivers (RXs), the proposed RX architecture employs a small 130-fF coupling capacitor to capture only transition information, eliminating the need for bulky …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3708634
Publisher: IEEE

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A 27-Gb/s/pin Inverter-Based Delay-Matched PAM-3 Transceiver With Pattern-Selective Switching Jitter Compensation for Die-to-Die Interfaces

A 27-Gb/s/pin Inverter-Based Delay-Matched PAM-3 Transceiver With Pattern-Selective Switching Jitter Compensation for Die-to-Die Interfaces 150 150
Author(s): Changmin Sim, Seongcheol Kim, Seungwoo Park, Junseob So, Hwaseok Shin, Taehwan Kim, Seon-Been Lee, Minkyun Shim, Chulwoo Kim

Abstract:

This article presents a 27-Gb/s/pin inverter-based delay-matched three-level pulse amplitude modulation (PAM-3) transceiver for short-reach die-to-die (D2D) interfaces. The proposed design uses two parallel, identical offset-programmable transimpedance amplifiers (TIAs) to independently generate two finely tunable PAM-3 reference levels with minimal parasitic loading, enabling multi-level signaling within a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3706449
Publisher: IEEE

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