equalization

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An 18.4-Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using Four-Phase Hybrid Timing Alignment and Dual Equalization

An 18.4-Gb/s/pin Simultaneous Bidirectional Transceiver for Post HBM4 Using Four-Phase Hybrid Timing Alignment and Dual Equalization 150 150
Author(s): Minchang Kim, Hankyu Chi, Sooncheol Kwon, Icsu Oh, Seulgi Kim, Heewoong Song, Daeho Yun, Jaehong Jeong, Daejoon Kim, Kichul Hong, Jeonghyun Park, Woo-Seok Choi, Hae-Kang Jung, Hoyoung Son, Inchul Jeong, Hyungsoo Kim, Jonghwan Kim

Abstract:

This letter presents a simultaneous bidirectional (SBD) transceiver for post HBM4. It is difficult to increase the data rate due to poor channel characteristics of the silicon interposer and the limited physical area of the IO in high-bandwidth memory (HBM) interface. SBD signaling is attractive because it doubles the per-pin …

Published in: IEEE Solid-State Circuits Letters
Page(s): 182 – 185
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3696268
Publisher: IEEE

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Modern Wireline Transceivers

Modern Wireline Transceivers 150 150
Author(s): Tony Chan Carusone, Timothy O. Dickson, Samuel Palermo, Sudip Shekhar, Mozhgan Mansuri

Abstract:

Over the past two decades, ever-increasing network bandwidth (BW) demands in data centers and high-performance computing systems have fueled exponential growth in per-lane serial link data rates. To keep up with this demand and enable faster communication over BW-limited electrical channels, wireline transceiver architectures and circuit topologies have rapidly evolved …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 395 – 422
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3642231
Publisher: IEEE

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A 112-Gb/s PAM4 Receiver With a Phase Equalization AFE in 7-nm FinFET

A 112-Gb/s PAM4 Receiver With a Phase Equalization AFE in 7-nm FinFET 150 150
Author(s): Huanan Guo, Yufeng Yao, Xiang Gao

Abstract:

To reduce the bit-error-rate (BER), equalizers are implemented in high-speed SerDes receivers (RX) to compensate for channel insertion loss and mitigate intersymbol interference (ISI). Conventional analog front-end (AFE) designs primarily focus on amplitude gain while neglecting the influence of phase shift. This brief presents a phase equalization (PEQ) AFE design …

Published in: IEEE Solid-State Circuits Letters
Page(s): 5 – 8
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3637833
Publisher: IEEE

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