Educational institutions

TexCAC: A Direct-Textile-Attachable Microcontroller Integrating 2-MB MRAM for the Command and Control of Advanced Smart Textiles

TexCAC: A Direct-Textile-Attachable Microcontroller Integrating 2-MB MRAM for the Command and Control of Advanced Smart Textiles 150 150

Abstract:

Advanced smart textiles (ASTs) are textile-integrated electronic systems that enable many applications, including healthcare, robotics, and IoT. ASTs contain a variety of electronic components to enable whole system functionality (batteries, sensors, SoCs, etc.), which all require orchestration from a central command-and-control (CAC) module. The primary functions of the CAC module …

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A Stress- and Temperature-Compensated TMR Current Sensor With ±0.13% Sensitivity Variation

A Stress- and Temperature-Compensated TMR Current Sensor With ±0.13% Sensitivity Variation 150 150

Abstract:

This article presents a high-precision tunnel magnetoresistance (TMR)-based non-contact current sensor with enhanced immunity to sensitivity drift. A background sensitivity stabilization loop (SSL) continuously regulates the TMR bias voltage to compensate intrinsic sensitivity variations. Through this closed-loop regulation, sensitivity drift of the TMR sensor induced by temperature, mechanical stress, …

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A Line-Connected Q-Sampler-Based Multi-Phase Hybrid Converter

A Line-Connected Q-Sampler-Based Multi-Phase Hybrid Converter 150 150

Abstract:

This article presents a line-connected Q-sampler-based (LQS) multi-phase (MP) hybrid converter for direct conversion from high-rail to point-of-load (PoL). The proposed topology uses an input-parallel switched-capacitor (SC) structure to support “ALL-ON” operation during load transients, while a “multi-source- ${V}_{\mathrm { X}}$ ” control decouples voltage conversion ratio (VCR) from phase count, …

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THz-TSI: A Terahertz Wireless Through-Silicon Interconnect Module for Advanced 3-D Integration Applications

THz-TSI: A Terahertz Wireless Through-Silicon Interconnect Module for Advanced 3-D Integration Applications 150 150

Abstract:

By vertically stacking device layers, advanced 3-D integration overcomes traditional planar scaling limits, delivering the bandwidth and power efficiency essential for modern artificial intelligence (AI) and high-performance computing (HPC) integrated systems. However, continued scaling of conventional through-silicon vias (TSVs) and microbumps presents critical bottlenecks due to inherent thermo-mechanical stress, complex …

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Raisu: A Radiation-Tolerant Neuromorphic Imager With In-Pixel Self-Healing and Unified Spiking Processing for Spaceborne Vision

Raisu: A Radiation-Tolerant Neuromorphic Imager With In-Pixel Self-Healing and Unified Spiking Processing for Spaceborne Vision 150 150

Abstract:

Spaceborne imaging systems operate under severe radiation and energy constraints, where single-event effects (SEEs), total ionizing dose (TID), and displacement damage dose (DDD) critically degrade reliability and performance. This work presents a radiation-tolerant neuromorphic imager prototype featuring a fully spike-based neuromorphic vision architecture with in-pixel self-healing capability and an integrated …

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A 96 × 64 SPAD LiDAR Sensor With 6× Imaging FoM Promotion by AI-Assisted Fusion of 2-D and Edge-Guided Sparse 3-D Detection

A 96 × 64 SPAD LiDAR Sensor With 6× Imaging FoM Promotion by AI-Assisted Fusion of 2-D and Edge-Guided Sparse 3-D Detection 150 150

Abstract:

Flash-mode direct time-of-flight (dToF) light detection and ranging (LiDAR) is widely adopted in autonomous systems and robotics due to its capability for accurate depth measurement and robustness under challenging lighting conditions. However, scaling single-photon avalanche diode (SPAD)-based dToF pixel arrays toward higher resolution 3-D imaging introduces significant challenges in …

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Current-Locked-Loop: A Circuit Topology for Reconfigurable High-Accuracy CMOS References

Current-Locked-Loop: A Circuit Topology for Reconfigurable High-Accuracy CMOS References 150 150

Abstract:

This article introduces a circuit topology for building reconfigurable, high-accuracy CMOS current and voltage references, namely, current-locked-loop (CLL). The CLL regulates the $V_{\mathrm {GS}}$ of a current source transistor and thus its current output using a digitally assisted feedback loop, thereby enabling higher order temperature coefficient (TC) compensation and …

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FSL-HDnn: A 40-nm Few-Shot On-Device Learning Accelerator With Integrated Feature Extraction and Hyperdimensional Computing

FSL-HDnn: A 40-nm Few-Shot On-Device Learning Accelerator With Integrated Feature Extraction and Hyperdimensional Computing 150 150

Abstract:

This article introduces FSL-HDnn, an energy-efficient accelerator that implements the end-to-end pipeline of feature extraction (FE) and on-device few-shot learning (FSL). The accelerator addresses fundamental challenges of on-device learning (ODL) for resource-constrained edge applications through two synergistic modules: a parameter-efficient feature extractor (FE) employing weight clustering and an FSL classifier …

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A 436–472 GHz 4-Element IF Beamforming Phased-Array Receiver in 65-nm CMOS

A 436–472 GHz 4-Element IF Beamforming Phased-Array Receiver in 65-nm CMOS 150 150

Abstract:

This article presents a 436–472GHz four-element intermediate-frequency (IF) beamforming phased-array receiver fabricated in 65-nm CMOS, targeting scalable terahertz (THz) phased-array systems. The proposed receiver adopts a two-step mixing scheme to reduce the area overhead of the IF beamforming implementation, thereby enhancing the array scalability at THz frequencies. Each receive channel …

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