dynamic power

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction 150 150

Abstract:

This article presents a 2-read/write (2RW) pseudo dual-port (PDP) static random access memory (SRAM) macro implemented in advanced 3nm Fin-FET technology, achieving a competitive bit density of 19.87Mbit/mm2 for advanced nodes. To address challenges in process scaling, reliability under process voltage temperature variations, and dynamic power consumption, two …

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A 3-nm FinFET 563-kbit 35.5-Mbit/mm2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode

A 3-nm FinFET 563-kbit 35.5-Mbit/mm2 Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode 150 150

Abstract:

This article presents a high-density (HD) 6T SRAM macro designed in 3-nm FinFET technology with an extended dual-rail (XDR) architecture, addressing active energy and leakage for mobile applications. Two key innovations are introduced: the delayed-wordline in write operation (DEWL) technique and a one-cycle latency low-leakage access mode (1-CLM). The XDR …

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