Domain-specific accelerator

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Verifica: Near-Memory Symbolic Interval Computing Formal Neural Network Verification Accelerator

Verifica: Near-Memory Symbolic Interval Computing Formal Neural Network Verification Accelerator 150 150
Author(s): Edward Jongyoon Choi, Byeongseon Choi, Jiho Chun, Minkyu Je, Bongjin Kim

Abstract:

Formal robustness verification of neural networks is essential for deploying machine learning (ML) systems in safety-critical applications. However, existing verification frameworks are predominantly software-based, incurring prohibitive computational costs and long runtimes, severely limiting scalability and practical deployment. Although symbolic interval analysis enables scalable over-approximate verification, its effectiveness is limited by …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3707324
Publisher: IEEE

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HUTAO: A Reconfigurable Homomorphic Processing UniT With Cache-Aware Operation Scheduling

HUTAO: A Reconfigurable Homomorphic Processing UniT With Cache-Aware Operation Scheduling 150 150
Author(s): Sijia Lu, Wenping Zhu, Bohan Yang, Jiajun Yang, Tongwei Dai, Chen Chen, Xiangdong Han, Jinjiang Yang, Hanning Wang, Min Zhu, Shaojun Wei, Aoyang Zhang, Leibo Liu

Abstract:

Fully homomorphic encryption (FHE) enables privacy-preserving machine learning (PPML) at the cost of intensive computational overhead, which necessitates the use of domain-specific accelerators. To achieve comprehensive support for leveled FHE, this article presents a reconfigurable multi-scheme FHE processor that supports both client-side encryption/decryption and server-side evaluation. First, a reconfigurable …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3657525
Publisher: IEEE

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