Digital calibration

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Current-Locked-Loop: A Circuit Topology for Reconfigurable High-Accuracy CMOS References

Current-Locked-Loop: A Circuit Topology for Reconfigurable High-Accuracy CMOS References 150 150
Author(s): Sining Pan, Xiaohan Liu, Ziyi Li, Minge Jiang, Yihang Cheng, Zhong Tang, Huaqiang Wu

Abstract:

This article introduces a circuit topology for building reconfigurable, high-accuracy CMOS current and voltage references, namely, current-locked-loop (CLL). The CLL regulates the $V_{\mathrm {GS}}$ of a current source transistor and thus its current output using a digitally assisted feedback loop, thereby enabling higher order temperature coefficient (TC) compensation and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3711071
Publisher: IEEE

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A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique

A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique 150 150
Author(s): Riccardo Moleri, Simone M. Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Abstract:

This work presents a digital-to-time converter (DTC)-based fractional-N digital phase-locked loop (PLL) designed to achieve simultaneously low jitter and low spurs. We introduce a novel DTC chopping technique that effectively mitigates fractional spurs, which we identify as predominantly arising from even-order nonlinearity invariable-slope (VS) DTCs. The proposed technique suppresses …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663074
Publisher: IEEE

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A Low-Jitter Fractional-N Digital PLL Using a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial-Based LMS Calibration

A Low-Jitter Fractional-N Digital PLL Using a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial-Based LMS Calibration 150 150
Author(s): Munjae Chae, Seheon Jang, Seungjae Lee, Jaehyouk Choi

Abstract:

This work presents a 10.0–11.5-GHz fractional- $N$ digital phase-locked loop (DPLL) using the quantization-error-compensating bang–bang phase detector (QEC-BBPD) that can minimize both the static delay ( $T_{\mathrm {S}}$ ) and the dynamic delay ( $T_{\mathrm {D}}$ ) required for removing the delta-sigma modulator’s ( $\Delta \Sigma $ M) quantization-error (Q-error). Since the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3611417
Publisher: IEEE

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