design–technology co-optimization (DTCO)

  • No Comments

Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multi-Tier CFET SRAM

Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multi-Tier CFET SRAM 150 150
Author(s): Yutian Zhang, Jiaquan Fang, Khawar Sarfraz, Mansun Chan

Abstract:

This work shows that multi-tier complementary FET (CFET) static random-access memory (SRAM) can decouple the area term from PPA-oriented transistor sizing. A topology-aware layout design is used to construct orthogonal and point-symmetric multi-tier CFET SRAM cells under 1-nm-class design rules, enabling high-density (HD), high-performance (HP), and high-current (HC) sizing at …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3709007
Publisher: IEEE

View on IEEE Xplore

  • No Comments

Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard-Cell Scaling

Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard-Cell Scaling 150 150
Author(s): Anup Ashok Kedilaya, Sirish Oruganti, Nishant Gupta, Xiuhao Zhang, Ilya Karpov, Mark A. Anders, Jaydeep P. Kulkarni

Abstract:

Advances in process technology enabling backside metals (BSMs) and contacts offer new design–technology co-optimization (DTCO) opportunities to further enhance power, performance, and area gains (PPA) in sub-3-nm nodes. This work exploits backside (BS) contact technology within standard cells to extend both signal and clock routing to BSM layers, …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 107 – 115
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3617784
Publisher: IEEE

View on IEEE Xplore

Search this website