Delta–sigma modulator (DSM)

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An 18.3-μW 108.3-dB DR Discrete-Time Delta-Sigma Modulator Using a Loop Filter Auto-Shift Technique

An 18.3-μW 108.3-dB DR Discrete-Time Delta-Sigma Modulator Using a Loop Filter Auto-Shift Technique 150 150
Author(s): Cong Wei, Ziqiang Peng, Lijie Huang, Jinze Lai, Rongshan Wei, Xiaoqiang Lu, Zhichao Tan

Abstract:

This article presents a discrete-time, third-order, single-loop, 17-level delta-sigma modulator (DSM) for high-dynamic-range sensor measurement applications, which employs a loop filter auto-shift (LFAS) technique. It uses an on-chip 1.5-bit Schmitt monitor to determine whether the input amplitude is large or small. The DSM automatically shifts to loop filter A for …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3684106
Publisher: IEEE

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A 14-b Energy-Efficient BW/Power Scalable CTDSM With a Frequency-Controlled Current Source

A 14-b Energy-Efficient BW/Power Scalable CTDSM With a Frequency-Controlled Current Source 150 150
Author(s): Xinjie Wu, Xiaopeng Yu, Nick Nianxiong Tan, Zhong Tang

Abstract:

This work presents a 14-bit energy-efficient bandwidth (BW)/power scalable continuous-time delta–sigma modulator (CTDSM) for sensor interfaces in IoT applications. To ensure low noise for small input signals and achieve BW/power scalability, it is built around Gm-C integrators biased via a linear frequency-controlled current source (FCCS). The FCCS …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 10
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3621527
Publisher: IEEE

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CORDIC-Less Digital Polar Transmitter Architecture Based on Delta-Sigma Modulator

CORDIC-Less Digital Polar Transmitter Architecture Based on Delta-Sigma Modulator 150 150
Author(s): Yuncheng Zhang, Zezheng Liu, Duo Li, Minzhe Tang, Yi Zhang, Hóngyè Huáng, Dingxin Xu, Waleed Madany, Ashbir Aviat Fadila, Wenqian Wang, Yuang Xiong, Daxu Zhang, Garry Pranata Kusuma, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada

Abstract:

Conventional digital polar transmitters (TXs) suffer from limited power efficiency and linearity due to the multi-bit nature of intermediate signals. This work proposes a digital polar TX architecture that avoids such drawbacks by reducing the bit count of TX signals. The proposed TX oversamples and quantizes multi-bit I/Q inputs …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3611233
Publisher: IEEE

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