A 112-Gb/s PAM4 Receiver With A Phase Equalization AFE in 7-nm FinFET https://sscs.ieee.org/wp-content/themes/movedo/images/empty/thumbnail.jpg 150 150 https://secure.gravatar.com/avatar/8fcdccb598784519a6037b6f80b02dee03caa773fc8d223c13bfce179d70f915?s=96&d=mm&r=g
Abstract:
To reduce the bit-error-rate(BER), equalizers are implemented in high-speed SerDes receivers (RX) to compensate for channel insertion loss and mitigate inter-symbol interference (ISI). Conventional analog front-end (AFE) designs primarily focus on amplitude gain while neglecting the influence of phase shift. This brief presents a phase equalization (PEQ) AFE design …