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Characterization and Modeling of Multilevel Analog ReRAM Synapses in the Sky130 Process

Characterization and Modeling of Multilevel Analog ReRAM Synapses in the Sky130 Process 150 150
Author(s): Irem Didin, Carl Brando, Ching-Yi Lin, Sahil Shah

Abstract:

Nonvolatile memory devices play a key role in enabling energy-efficient computing. Among them, analog nonvolatile memories such as resistive random access memory (ReRAM) offer high density and low power compared to conventional digital memories. However, their analog nature introduces device-level variability that impacts computational accuracy. This work presents the characterization …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 27 – 35
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3670667
Publisher: IEEE

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A 7056-PPI Pixel Circuit With Low-Leakage Structure for Active-Matrix Monochrome Micro-LED Displays

A 7056-PPI Pixel Circuit With Low-Leakage Structure for Active-Matrix Monochrome Micro-LED Displays 150 150
Author(s): Chih-Lung Lin, Cheng-Han Ke, Yu-Chang Chiu, Yuan-Yu Lai, Yi-Chien Chen, Cheng-Rui Lu, Yu-Hsiang Fu, Chih-Chuan Huang

Abstract:

This work presents a 5T2C pixel circuit for active-matrix (AM) micro-displays in near-eye display applications. The circuit supports monochrome micro light-emitting diode (micro-LED) displays with ultrahigh resolution of 7056 pixels per inch (PPI). The circuit is designed and fabricated based on medium-voltage (MV) devices from the 55-nm high-voltage (HV) CMOS …

Published in: IEEE Solid-State Circuits Letters
Page(s): 89 – 92
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3667520
Publisher: IEEE

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On-Chip Charge-Trap-Transistor-Based Mismatch Calibration of an 8-Bit Thermometer Current-Source DAC

On-Chip Charge-Trap-Transistor-Based Mismatch Calibration of an 8-Bit Thermometer Current-Source DAC 150 150
Author(s): Mohammadreza Zeinali, Sudhakar Pamarti

Abstract:

This letter presents an on-chip mismatch calibration technique for current-source digital-to-analog converters (DACs) using charge-trap transistors (CTTs) in 22-nm FDSOI technology. The proposed method exploits programmable threshold voltage (VTH) shifts in CTTs to locally tune the current of near-minimum-sized devices without external trimming. A compact 8-bit thermometer DAC is implemented …

Published in: IEEE Solid-State Circuits Letters
Page(s): 53 – 56
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3656261
Publisher: IEEE

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A 10.2 V 8-Channel Neural Stimulator With Nearly Constant Efficiency Across 90% Current Range and a TDM ADC-Based One-Shot Charge Balancing With < 6 mV Residue

A 10.2 V 8-Channel Neural Stimulator With Nearly Constant Efficiency Across 90% Current Range and a TDM ADC-Based One-Shot Charge Balancing With < 6 mV Residue 150 150
Author(s): Alin Thomas Tharakan, Cong Huang, Yiheng Fu, Horacio Londoño Ramírez, Stéphanie P. Lacour, Mahsa Shoaran

Abstract:

This letter presents an 8-channel current-mode stimulator achieving a ±10.2 V voltage compliance in a standard CMOS process, supporting up to 4.5 mA stimulation current per channel. The proposed dynamic charge pump (DCP), which adaptively sizes its switches based on the stimulation current, helps achieve ~15% higher power efficiency at low currents compared …

Published in: IEEE Solid-State Circuits Letters
Page(s): 49 – 52
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3653014
Publisher: IEEE

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220 GHz, 8.5-dBm Saturated Output Power Wideband Power Amplifier in SiGe BiCMOS

220 GHz, 8.5-dBm Saturated Output Power Wideband Power Amplifier in SiGe BiCMOS 150 150
Author(s): Xun Chen, Jonas Winkelhake, Muh-Dey Wei, Renato Negra

Abstract:

This letter presents a broadband $G$ -band power amplifier (PA) designed in a 130-nm silicon-germanium (SiGe) bipolar complementary metal-oxide-semiconductor technology. Unlike dual-band matching and staggered tuning techniques to obtain large operation bandwidth (BW), we propose a common broadband amplification stage in this work for its flexibility. In each stage, inductive …

Published in: IEEE Solid-State Circuits Letters
Page(s): 17 – 20
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3646267
Publisher: IEEE

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PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI

PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI 150 150
Author(s): Jakob Finkbeiner, Raphael Nägele, Manuel Wittlinger, Markus Grözing, Manfred Berroth, Georg Rademacher

Abstract:

Analog computing offers intrinsic energy and latency benefits that makes it attractive for real-time and edge applications. Conventional analog accelerators suffer from repeated conversions between analog and digital domain, which degrades efficiency and throughput. We propose an all-analog pipelined neural network accelerator architecture in 22 nm fully-depleted silicon-on-insulator (FD-SOI) complementary metal-oxide-semiconductor (…

Published in: IEEE Solid-State Circuits Letters
Page(s): 365 – 368
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3627274
Publisher: IEEE

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A Compact, Highly-Digital Sensor-Fusion-Based Joint V dd-Temperature Sensor for SoC Thermal Management

A Compact, Highly-Digital Sensor-Fusion-Based Joint V dd-Temperature Sensor for SoC Thermal Management 150 150
Author(s): Hikmet Seha Öztürk, Julian Arenas, Carlos Tokunaga, Nasser Kurd, Visvesh S. Sathe

Abstract:

This article presents a fine-grained thermal sensing network for thermal management in SoCs. Sensor nodes in this network are made up of joint supply voltage ( $V_{\mathrm {dd}}$ ) and temperature ( $T$ ) sensors, which are compact and highly digital. Measurements from these simple but imperfect sensors are jointly processed to extract …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3621280
Publisher: IEEE

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A Linear Dynamic Voltage Scaling Technique With Adaptive Minimum Voltage Headroom Tracking for Implantable Neurostimulation

A Linear Dynamic Voltage Scaling Technique With Adaptive Minimum Voltage Headroom Tracking for Implantable Neurostimulation 150 150
Author(s): Kai Cui, Honglei Xu, Yingduo Duan, Yan Lu, Xiaoya Fan, Yanzhao Ma

Abstract:

This letter presents a linear dynamic voltage scaling (DVS) technique using a dual-loop multistage charge-pump maintaining the minimum voltage headroom for implantable neurostimulation. By adopting an analog DVS with adaptive feedback divider, the stimulus current source could be always kept operating at the boundary of the saturation region and the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 261 – 264
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3608096
Publisher: IEEE

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MIX-ACIM: A 28-nm Mixed-Precision Analog Compute-in-Memory With Digital Feature Restoration for Vector-Matrix Multiplication

MIX-ACIM: A 28-nm Mixed-Precision Analog Compute-in-Memory With Digital Feature Restoration for Vector-Matrix Multiplication 150 150
Author(s): Wei-Chun Wang, Shida Zhang, Laith Shamieh, Narasimha Vasishta Kidambi, Isha Chakraborty, Saibal Mukhopadhyay

Abstract:

A mixed-precision analog compute-in-memory (Mix-ACIM) is presented for mixed-precision vector-matrix multiplication (VMM). The design features an all-analog current-domain fixed-point (FxP) VMM with floating-point conversion and feature restoration. A 28 nm CMOS test chip shows 41 TOPS/W and 24 TOPS/mm2 for FxP (8-bit input/weight and 12-bit output) and 24.18 TFLOPS/W and 3.3 …

Published in: IEEE Solid-State Circuits Letters
Page(s): 213 – 216
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3590757
Publisher: IEEE

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