Common Information Model (computing)

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Device–Circuit–System Co-Design of Reconfigurable Oxide-Semiconductor 2T Non-Volatile Gain-Cell Memory and Sandwich-3D LLM Accelerator

Device–Circuit–System Co-Design of Reconfigurable Oxide-Semiconductor 2T Non-Volatile Gain-Cell Memory and Sandwich-3D LLM Accelerator 150 150
Author(s): Luqi Zheng, Chang Niu, Shuting Du, Sumi Lee, Amir Massah Bavani, Zehao Lin, Peide D. Ye, Haitong Li

Abstract:

In this work, we present an oxide-semiconductor (OS)-based 2T non-volatile gain-cell (NVGC) memory and a “sandwich 3D” stacking scheme, co-designed using ALD InOx OSFETs and OS-FeFETs, for efficient large language model (LLM) acceleration. The new 2T-NVGC enables native, in-memory reconfiguration of static/dynamic kernels for Transformers and context-switching workloads, …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740041
Publisher: IEEE

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SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators

SEAL: Multitenant Security-Aware Layer Mapping for Heterogeneous 3-D CiM Accelerators 150 150
Author(s): Pragya Sharma, Sriniketh Purisai Ramanujam, Ashish Reddy Bommana, Hossein Pourmehrani, Naghmeh Karimi, Farshad Firouzi, Krishnendu Chakrabarty

Abstract:

Heterogeneous 3-D compute-in-memory (CiM) architectures have emerged as an efficient acceleration paradigm for deep neural network (DNN) inference by leveraging the complementary characteristics of diverse memory technologies enabled through 3-D integration. Prior work has focused on architectural efficiency and workload-mapping optimization, leaving the security implications of heterogeneous CiM systems largely …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 205 – 213
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3734047
Publisher: IEEE

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SMoLPU: An Energy-Efficient Sparse Mixture-of-Experts-Based Speculative Decoding Language Processing Unit

SMoLPU: An Energy-Efficient Sparse Mixture-of-Experts-Based Speculative Decoding Language Processing Unit 150 150
Author(s): Sangwoo Ha, Jingu Lee, Youngjin Moon, Sunjoo Whang, Wooyoung Jo, Gwangtae Park, Sangjin Kim, Soyeon Um, Junha Ryu, Yurim Jo, Hoi-Jun Yoo

Abstract:

Reasoning strategies such as chain-of-thought improve the accuracy of large language models (LLMs) but lengthen decoding sequences, inflating external memory access (EMA) on mobile devices. Numerous optimizations have been explored to reduce EMA, from conventional techniques such as group quantization and channel-wise pruning to sparse mixture-of-experts (MoE) and speculative decoding (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3726852
Publisher: IEEE

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A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI

A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI 150 150
Author(s): Jiho Chun, Byeongseon Choi, Edward Jongyoon Choi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je

Abstract:

Computing in memory (CIM) has emerged as a promising architecture that can significantly reduce power consumption and latency in edge artificial intelligence (AI) devices. For battery-constrained edge devices, non-volatile memories (NVMs) are ideal due to their ability to retain neural network parameters even when powered down, ensuring rapid response time …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3717139
Publisher: IEEE

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MTDiff: A Multi-Task Diffusion Accelerator With Bandwidth-Aware Memory Partition and Efficient Digital Compute-in-Memory

MTDiff: A Multi-Task Diffusion Accelerator With Bandwidth-Aware Memory Partition and Efficient Digital Compute-in-Memory 150 150
Author(s): Jiaqi Zhou, Yiqi Jing, Yiyang Sun, Siyuan He, Le Ye, Tianyu Jia

Abstract:

Initially applied to image synthesis, diffusion models have rapidly expanded into various content generation tasks, such as 3-D scene reconstruction and video generation, due to the superior generative quality. Based on our observations, the imbalanced operational intensities across diffusion model layers lead to suboptimal hardware utilization due to inadequate bandwidth …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3718715
Publisher: IEEE

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APM-CIM: An Array Partition Multi-Macro CIM System With Dynamic Sparse Approximation for Neural Network Edge Applications

APM-CIM: An Array Partition Multi-Macro CIM System With Dynamic Sparse Approximation for Neural Network Edge Applications 150 150
Author(s): Bojun Zhang, Jinkai Wang, Zekun Wang, Xianan Zhu, Zhengkun Gu, Ziyuan Guo, Zhizhong Zhang, Kun Zhang, Weisheng Zhao, Yue Zhang

Abstract:

Computing-in-memory (CIM) has been widely investigated as a solution to the von Neumann bottleneck to reduce data transfer between memory and processor. However, existing CIM macros for neural network (NN) edge applications still suffer from high latency and energy consumption due to the correlation between data precision and the number …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3720241
Publisher: IEEE

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A 28-nm Sign-Bit-Embedded Bit-Parallel SRAM Compute-in-Memory Macro With Stage-Wise-Enabled Transition-Counting-Lines and Accumulators for Edge-AI Devices

A 28-nm Sign-Bit-Embedded Bit-Parallel SRAM Compute-in-Memory Macro With Stage-Wise-Enabled Transition-Counting-Lines and Accumulators for Edge-AI Devices 150 150
Author(s): Yunlong Liu, Lichen Feng, Lin Wu, Dong Li, Zhangming Zhu

Abstract:

Computing-in-memory (CIM) architectures are promising for edge-AI devices, as they mitigate the von Neumann bottleneck and reduce data movement. Bit-parallel CIM macros with direct memory mapping and low toggle rate are well-suited for computing systems. However, severe routing congestion, inefficient signed computation, and unnecessary toggling of intermediate signals in local …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3718075
Publisher: IEEE

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A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS

A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS 150 150
Author(s): Saideep Cherukuri, N. V. Kidambi, W. C. Wang, I. Chakraborty, S. Zhang, L. Shamieh, J. B. Steinberg, S. Mukhopadhyay

Abstract:

Mixed-signal CIM (MS-CIM) faces bit-cell nonlinearity, poor linearity at high frequency, and throughput limits. We present a hybrid pipelined current-domain MS-CIM macro featuring bit-cell matched linearization interface (BMLI) and loop-unrolled successive approximation refinement (SAR) ADC fabricated in 28-nm CMOS. A $256{\,}\times {\,}256$ SRAM array with 8-bit inputs, 8-bit weights achieve 10.16-TOPS …

Published in: IEEE Solid-State Circuits Letters
Page(s): 174 – 177
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697990
Publisher: IEEE

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A 28-nm PVT Inner-Tracking Time-Domain Compute-In-Memory Macro for Edge-AI Devices

A 28-nm PVT Inner-Tracking Time-Domain Compute-In-Memory Macro for Edge-AI Devices 150 150
Author(s): Yuanzhe Zhao, Yuheng Wang, Heng Xie, Zijian Wang, Rui P. Martins, Chi-Hang Chan, Minglei Zhang

Abstract:

This article presents an energy-efficient and process-, voltage-, and temperature (PVT)-robust time-domain (TD) compute-in-memory (CIM) macro for edge artificial intelligence (AI) devices. It features: 1) a PVT inner-tracking (PIT) technique that aligns the PVT responses of TD computation and TD quantization, delivering inherent robustness without incurring extra power or circuit …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3691189
Publisher: IEEE

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