CMOS technology

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Benchmarking of Emerging Material-Based TCAMs

Benchmarking of Emerging Material-Based TCAMs 150 150
Author(s): Ashwin Tunga, Junzhe Kang, Zijing Zhao, Ankit Shukla, Wenjuan Zhu, Shaloo Rakheja

Abstract:

This work presents a comprehensive benchmarking of ternary content-addressable memory (TCAM) implementations using timing-accurate SPICE simulations, systematically comparing conventional CMOS designs with emerging device technologies, including magnetic tunnel junctions (MTJs), ferroelectric tunnel junctions (FTJs), ferroelectric field-effect transistors (FeFETs), and 2-D reconfigurable field-effect transistors (2D RFETs). Key performance metrics, including search …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 104 – 112
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3687143
Publisher: IEEE

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The Impact of Magnetic Field on Defective FDSOI and FinFET Devices

The Impact of Magnetic Field on Defective FDSOI and FinFET Devices 150 150
Author(s): Munazza Sayed, Hussam Amrouch

Abstract:

This article explores the efficacy of a unique defect detection mechanism for the FinFET and FDSOI transistors: magnetomodulation of drain current. Using multiphysics technology CAD (TCAD), we model the impact of static and transient magnetic fields on drain current in the following defect-free and defective devices: 1) FDSOI with interface trap …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 113 – 119
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3686904
Publisher: IEEE

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A 550-μW Capacitor-Assisted Transformer-Based VCO Achieving 204-dBc/Hz FoMA at 1-MHz Frequency Offset

A 550-μW Capacitor-Assisted Transformer-Based VCO Achieving 204-dBc/Hz FoMA at 1-MHz Frequency Offset 150 150
Author(s): Teng-Shen Yang, Liang-Hung Lu

Abstract:

This letter presents a capacitor-assisted transformer (CTF)-based voltage-controlled oscillator (VCO) that achieves a low flicker-noise corner with submilliwatt power consumption and compact chip area. By introducing a small assisting capacitor into the transformer, the higher order tank impedance is reshaped from the second-resonance region toward the third-resonance region, resulting …

Published in: IEEE Solid-State Circuits Letters
Page(s): 150 – 153
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3690818
Publisher: IEEE

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A 6.8–14-GHz Ring-Based Sampling-PLL Achieving 69.3-fs Jitter Under 50-mV Supply Noise

A 6.8–14-GHz Ring-Based Sampling-PLL Achieving 69.3-fs Jitter Under 50-mV Supply Noise 150 150
Author(s): Mahmoud A. Khalil, Mohamed Badr Younis, Ruhao Xia, Ahmed E. Abdelrahman, Tianyu Wang, Kyu-Sang Park, Pavan Kumar Hanumolu

Abstract:

This article presents a type-III wide-bandwidth ring-oscillator-based analog phase-locked loop (PLL) optimized for low-jitter performance in noisy supply environments. The design uses an 812.5-MHz reference frequency and a high-gain sampling phase detector to achieve a closed-loop bandwidth over 100 MHz, effectively reducing the intrinsic phase noise of the ring oscillator. To …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3683111
Publisher: IEEE

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An 800-MS/s 13-b 2× TI Pipelined-SAR ADC With Rapid Digital Amplification

An 800-MS/s 13-b 2× TI Pipelined-SAR ADC With Rapid Digital Amplification 150 150
Author(s): Peizhe Li, Danfeng Zhai, Qi Liu, Chixiao Chen

Abstract:

This work proposes a rapid digital amplification (RDA) with residue-aware reference, offering an equivalent open-loop (OL) gain enhancement of 25 dB and reducing the interstage gain error (ISGE)-induced SNR degradation by 20 dB, with an extra amplification latency of only 200 ps. It is implemented in an 800-MS/s 13-b two-way time-interleaved (…

Published in: IEEE Solid-State Circuits Letters
Page(s): 137 – 140
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3684735
Publisher: IEEE

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Self-Enabled Write Assist Cells for High-Density SRAM in Resistance-Dominated Technology Node

Self-Enabled Write Assist Cells for High-Density SRAM in Resistance-Dominated Technology Node 150 150
Author(s): Minjune Yeo, Seungjae Yei, Keonhee Cho, Giseok Kim, Mingu Kang, Seong-Ook Jung

Abstract:

As technology scaling increases interconnect resistance, writeability degradation in static random access memory (SRAM) becomes critical. This article presents a self-enabled write assist cell (SEWAC) that mitigates writeability degradation caused by increased bitline resistance (R ${}_{\mathrm {BL}}$ ) without requiring timing control. The SEWAC has a cell-compatible layout with the standard 6…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3681916
Publisher: IEEE

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A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction 150 150
Author(s): Tomotaka Tanaka, Koji Nii, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Abstract:

This article presents a 2-read/write (2RW) pseudo dual-port (PDP) static random access memory (SRAM) macro implemented in advanced 3nm Fin-FET technology, achieving a competitive bit density of 19.87Mbit/mm2 for advanced nodes. To address challenges in process scaling, reliability under process voltage temperature variations, and dynamic power consumption, two …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3682256
Publisher: IEEE

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A Novel VGSOT-pMTJ Write Circuit for Hybrid CMOS/MTJ CIM Architecture

A Novel VGSOT-pMTJ Write Circuit for Hybrid CMOS/MTJ CIM Architecture 150 150
Author(s): Prashanth Barla, Ramya Moodakare

Abstract:

Hybrid computation-in-memory (CIM) architecture has emerged as the most promising alternative to overcome the drawbacks of the conventional CMOS-only devices used in the conventional von-Neumann architecture. In the hybrid CIM architecture, a pair of perpendicular magnetic tunnel junctions (pMTJs) is used to store one bit of information. Though there are …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 65 – 69
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3679830
Publisher: IEEE

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A Bidirectional Neuromodulation Chipset With Algorithm-Aware AFE Optimization and High-Voltage-Compliant Stimulation

A Bidirectional Neuromodulation Chipset With Algorithm-Aware AFE Optimization and High-Voltage-Compliant Stimulation 150 150
Author(s): Xiaohua Huang, Hoda Yassin, Beatriz Lafuente Alcazar, Arash Akhoundi, Dante G. Muratore

Abstract:

This work presents a bidirectional neuromodulation chipset with 64-channel neural analog front-end (AFE), and a four-channel current stimulator. The chipset employs a heterogeneous architecture, combining a 28-nm low-voltage (LV) CMOS process for the AFE and the digital backend (DBE) to improve area and power efficiency, with a 180-nm high-voltage (HV) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3650066
Publisher: IEEE

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