CMOS process

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A 500 MS/s Robust 2b/cycle Pipelined-SAR ADC Achieving 64.6-dB SNDR and 82.6-dB SFDR With Linearity Enhancement Techniques

A 500 MS/s Robust 2b/cycle Pipelined-SAR ADC Achieving 64.6-dB SNDR and 82.6-dB SFDR With Linearity Enhancement Techniques 150 150
Author(s): Qiang Yu, Zheng Zhu, Lulu Zhang, Qin Huang, Yao Feng, Chao Liang, Biao Hu, Ling Du, Rongbin Yang, Shuangyi Wu, Qiang Li

Abstract:

This letter presents a 14-bit 500-MS/s 3-stage pipelined successive approximation register (SAR) analog-to-digital converter (ADC). By exploiting robust 2b/cycle SAR ADCs, this ADC incorporates significant voltage and time redundancy. High SFDR is achieved through several linearity enhancement techniques. First, a DAC splitting technique addresses the common-mode voltage matching …

Published in: IEEE Solid-State Circuits Letters
Page(s): 9 – 12
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3639322
Publisher: IEEE

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A 76.9 ppm/K Nano-Watt PVT-Insensitive CMOS Voltage Reference Operating From 4 to 300 K for Integrated Cryogenic Quantum Interface

A 76.9 ppm/K Nano-Watt PVT-Insensitive CMOS Voltage Reference Operating From 4 to 300 K for Integrated Cryogenic Quantum Interface 150 150
Author(s): Jing Wang, Jun He, Man-Kay Law, Xinzhe Wang, Futian Liang, Lin Cheng

Abstract:

This work proposes a temperature and process-compensated low-power Cryo-CMOS voltage reference without trimming for quantum integrated interface, which is capable of operating continuously from room temperature (RT) down to cryogenic temperatures. By compensating for the main accuracy limiting factors including the process dependence of the transistor threshold voltage, device mismatch …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 3242 – 3256
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3530472
Publisher: IEEE

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