Clocks

  • No Comments

A Fully Integrated Digital LDO With Adaptive Sampling and Statistical Comparator Selection

A Fully Integrated Digital LDO With Adaptive Sampling and Statistical Comparator Selection 150 150
Author(s): Shun Yamaguchi, Takashi Hisakado, Osami Wada, Mahfuzul Islam

Abstract:

Digital LDOs are gaining attention for their operation with small output capacitance. Adaptive sampling with a large frequency scaling ratio is required for fast transient response with low-power operation. Furthermore, the design of a fluctuation detector to deal with large load steps is important. This letter describes an adaptive-sampling digital …

Published in: IEEE Solid-State Circuits Letters
Page(s): 163 – 166
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3385233
Publisher: IEEE

View on IEEE Xplore

  • No Comments

INTIACC: A Programmable Floating-Point Accelerator for Partial Differential Equations

INTIACC: A Programmable Floating-Point Accelerator for Partial Differential Equations 150 150
Author(s): Paul Xuanyuanliang Huang, Yannis Tsividis, Mingoo Seok

Abstract:

This article presents a 32-bit floating-point (FP32) programmable accelerator for solving a wide range of partial differential equations (PDEs) based on numerical integration methods. Compared to prior works that have fixed-point systems and are only applicable to specific types of PDEs, our proposed, integration accelerator for PDEs, named INTIACC, accelerator …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3379308
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 50-Gb/s Multicarrier Transmitter Using DAC-Based Polar Drivers in 22-nm FinFET

A 50-Gb/s Multicarrier Transmitter Using DAC-Based Polar Drivers in 22-nm FinFET 150 150
Author(s): Il-Min Yi, Srujan Kumar Kaile, Yuanming Zhu, Julian Camilo Gomez Diaz, Sebastian Hoyos, Samuel Palermo

Abstract:

A digital-to-analog converter (DAC)-based polar transmitter (TX) is proposed for multicarrier signaling in wireline applications. The proposed TX achieves a 50-Gb/s total data rate with maximized spectral efficiency by using three parallel 5-GS/s DAC-based drivers and two orthogonal carriers of 5 and 10 GHz. The three DAC-based drivers operating …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2024
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2024.3376079
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 6.4-Gb/s/pin nand Flash Memory Multichip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems

A 6.4-Gb/s/pin nand Flash Memory Multichip Package Employing a Frequency Multiplying Bridge Chip for Scalable Performance and Capacity Storage Systems 150 150
Author(s): Shinichi Ikeda, Akira Iwata, Goichi Otomo, Tomoaki Suzuki, Hiroaki Iijima, Mikio Shiraishi, Shinya Kawakami, Masatomo Eimitsu, Yoshiki Matsuoka, Kiyohito Sato, Shigehiro Tsuchiya, Yoshinori Shigeta, Takuma Aoyama

Abstract:

This letter describes a NAND flash memory multichip package (NAND MCP) incorporating a developed LSI interface (IF) Chip (Bridge Chip) in which the IF to and from the solid-state drive (SSD) controller has twice the speed as that of the IF to and from the NAND dies even with multiple …

Published in: IEEE Solid-State Circuits Letters
Page(s): 115 – 118
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3377263
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A 90 µW at 1 fps and 1.33 mW at 30 fps 120-dB Intrascene Dynamic Range 640 × 480 Stacked Image Sensor for Autonomous Vision Systems

A 90 µW at 1 fps and 1.33 mW at 30 fps 120-dB Intrascene Dynamic Range 640 × 480 Stacked Image Sensor for Autonomous Vision Systems 150 150
Author(s): Pierre-François Rüedi, Riccardo Quaglia, Hans-Rudolf Graf

Abstract:

We present an ultralow-power high dynamic range (DR) image sensor dedicated to autonomous vision systems, produced in a back illuminated 65 nm/40 nm stacked process and based on a time-to-digital pixel with in-pixel A/D conversion and data memory. Key to the low-power consumption is a new in-pixel comparator without dc …

Published in: IEEE Solid-State Circuits Letters
Page(s): 106 – 109
Year of Publication: 2024
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2024.3370797
Publisher: IEEE

View on IEEE Xplore

Search this website