Clocks

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A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS

A 64-Gb/s/pin 0.25-pJ/b Single-Ended Short-Reach PAM4 Transceiver in 28-nm CMOS 150 150
Author(s): Kshitiz Tyagi, Kunbo Ma, Joung Won Park, Behzad Razavi

Abstract:

We present a transceiver architecture for single-ended PAM4 signaling, introducing an inverter-based active-inductor terminated front-end that obviates the need for further equalizer stages, substantially reducing power and area. Realized in 28-nm CMOS technology, the 4-lane link operates at 64 Gb/s/pin with a bit error rate less than 10-12 while …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3721808
Publisher: IEEE

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A 6-bit Serializer With Integrated Manchester Encoder Using Flexible a-IGZO TFT Technology

A 6-bit Serializer With Integrated Manchester Encoder Using Flexible a-IGZO TFT Technology 150 150
Author(s): Suyash Shrivastava, Pydi Ganga Bahubalindruni

Abstract:

This article presents an experimental characterization of a novel 6-bit parallel-to-serial data converter integrated with a Manchester encoder. The system comprises an on-chip digital logic block that generates six mutually nonoverlapping control signals ( $\phi _{0-5}$ ) and three 120° phase-shifted clock signals to drive the switching transistors in the serializer and the …

Published in: IEEE Solid-State Circuits Letters
Page(s): 194 – 197
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3707465
Publisher: IEEE

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A 300-μW BLE-Compliant Packet-Based Data-Agnostic Clock-Harvesting RX Achieving −85/−70 dBm Sensitivity for ±40/±15 ppm Accuracy

A 300-μW BLE-Compliant Packet-Based Data-Agnostic Clock-Harvesting RX Achieving −85/−70 dBm Sensitivity for ±40/±15 ppm Accuracy 150 150
Author(s): Maryam Dodangeh, Mark S. Oude Alink, Jan Prummel, Bram Nauta

Abstract:

An ultralow-power Bluetooth low energy (BLE)-compliant crystal-less clock-harvesting receiver is presented that uses the BLE advertising packets (APs) to calibrate an on-chip frequency reference with ±400 ppm initial frequency offset. The proposed front-end, fabricated in 22 nm FDSOI, is capable of pushing the frequency accuracy of the reference further to below ±40/±15 …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3718973
Publisher: IEEE

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BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoMREF of −247.9 dB at 3 GHz With a Ring Oscillator

BASS-PLL: A Bandwidth Augmented Sub-Sampling PLL Achieving a Wide Bandwidth Above 30% of the Reference Frequency and a Worst Case FoMREF of −247.9 dB at 3 GHz With a Ring Oscillator 150 150
Author(s): Tong Zhang, Yiwen Zhang, Xueke Cai, Weihao Jie, Yanling Zheng, Deyong Li, Yang Zhao, Yongfu Li, Honglan Jiang, Patrick P. Mercier, Hui Wang

Abstract:

This work presents a bandwidth augmented sub-sampling phase-locked loop (BASS-PLL) architecture that features simultaneous out-of-band noise suppression by direct and multipath sampling of the ring oscillator’s (ROs) output and in-band noise suppression via an intrinsic sub-sampling mechanism, ultimately combining the benefits of over-sampling PLLs (OS-PLLs) and sub-sampling PLLs (SS-PLLs) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 847 – 859
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3640726
Publisher: IEEE

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TD-dAJC: A 100 MS/s 2 pJ/Pixel Time-Domain Weight and Integrating-MAC-Based Direct Analog to MJPEG Compression for Video Sensor Nodes

TD-dAJC: A 100 MS/s 2 pJ/Pixel Time-Domain Weight and Integrating-MAC-Based Direct Analog to MJPEG Compression for Video Sensor Nodes 150 150
Author(s): Harshit Naman, Gourab Barik, Yudhajit Ray, Shreyas Sen

Abstract:

Always-on, high-quality video sensors are increasingly required in wearables, surveillance, and Internet-of-Things (IoT) devices, where stringent energy constraints make efficient in-sensor compression necessary. These systems must support high-definition (HD) and 4 K video, yet conventional digital video compression pipelines consume significant power because high-speed analog-to-digital converters (ADCs) must digitize every pixel, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3712196
Publisher: IEEE

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A 12-Gb/s Source-Synchronous Single-Ended PAM-4 Transceiver With Background Adaptive Crosstalk Equalization in 28-nm CMOS

A 12-Gb/s Source-Synchronous Single-Ended PAM-4 Transceiver With Background Adaptive Crosstalk Equalization in 28-nm CMOS 150 150
Author(s): DongArm Shin, Kuy Youn Chung, Sihoon Yang, SeongHwan Cho

Abstract:

This article presents a background adaptive crosstalk (XT) equalization technique for a single-endedfour-level pulse amplitude modulation (PAM-4) interface to maintain accurate XT cancellation (XTC) under environmental variations. A least-mean-square (LMS) adaptation loop adjusts the XT equalizer using a source-synchronous clock as an aggressor reference uncorrelated with the victim. At the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3712021
Publisher: IEEE

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A 27-Gb/s/pin Inverter-Based Delay-Matched PAM-3 Transceiver With Pattern-Selective Switching Jitter Compensation for Die-to-Die Interfaces

A 27-Gb/s/pin Inverter-Based Delay-Matched PAM-3 Transceiver With Pattern-Selective Switching Jitter Compensation for Die-to-Die Interfaces 150 150
Author(s): Changmin Sim, Seongcheol Kim, Seungwoo Park, Junseob So, Hwaseok Shin, Taehwan Kim, Seon-Been Lee, Minkyun Shim, Chulwoo Kim

Abstract:

This article presents a 27-Gb/s/pin inverter-based delay-matched three-level pulse amplitude modulation (PAM-3) transceiver for short-reach die-to-die (D2D) interfaces. The proposed design uses two parallel, identical offset-programmable transimpedance amplifiers (TIAs) to independently generate two finely tunable PAM-3 reference levels with minimal parasitic loading, enabling multi-level signaling within a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3706449
Publisher: IEEE

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A 24.5–45.2-GHz Low-Jitter Compact Differentially Injection-Locked Clock Multiplier With Folded-Inductor-Based Magnetic-Flux Cancellation

A 24.5–45.2-GHz Low-Jitter Compact Differentially Injection-Locked Clock Multiplier With Folded-Inductor-Based Magnetic-Flux Cancellation 150 150
Author(s): Feifan Hong, Jiawen Chen, Pingda Guan, Sayan Kumar, Robert Bogdan Staszewski, Teerachot Siriburanon

Abstract:

In this article, we present a differentially injection-locked clock multiplier (ILCM) featuring an ultra-wide frequency tuning range (TR) and low jitter, achieved through a compact folded-inductor-based magnetic-flux cancellation technique. A co-designed series-LC dual-mode quadrature ring oscillator (QRO) and edge-combining frequency doubler operating in the mm-wave band jointly extend the TR …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1410 – 1424
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3640957
Publisher: IEEE

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A Ka-Band Time-Modulated Phase-Invariant Variable-Gain Amplifier With 30-dB Gain Tuning Based on Duty-Cycle Control

A Ka-Band Time-Modulated Phase-Invariant Variable-Gain Amplifier With 30-dB Gain Tuning Based on Duty-Cycle Control 150 150
Author(s): Dongfan Xu, Minzhe Tang, Haiyun Gu, Yuxuan Liu, Yilun Chen, Ziyuan Ren, Minghao Fan, Daxu Zhang, Yi Zhang, Duo Li, Zheng Li, Zezheng Liu, Chun Wang, Yudai Yamazaki, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada

Abstract:

This article presents a time-modulated variable-gain amplifier (VGA) employing a clock-sampling topology governed by a duty-cycle control (DCC) loop. By modulating the effective operation time of the amplifier rather than altering its RF bias conditions, for precise tuning of the clock duty cycle, enabling phase consistency at millimeter-wave frequencies. The …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3695362
Publisher: IEEE

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