chopping

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A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique

A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique 150 150
Author(s): Riccardo Moleri, Simone M. Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino

Abstract:

This work presents a digital-to-time converter (DTC)-based fractional-N digital phase-locked loop (PLL) designed to achieve simultaneously low jitter and low spurs. We introduce a novel DTC chopping technique that effectively mitigates fractional spurs, which we identify as predominantly arising from even-order nonlinearity invariable-slope (VS) DTCs. The proposed technique suppresses …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 17
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3663074
Publisher: IEEE

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A 45-V Auto-Zero-Stabilized Chopper Instrumentation Amplifier With 1.8- μ V Offset, 33.5- μ V Ripple, and 42-V Common-Mode Input Range

A 45-V Auto-Zero-Stabilized Chopper Instrumentation Amplifier With 1.8- μ V Offset, 33.5- μ V Ripple, and 42-V Common-Mode Input Range 150 150
Author(s): Jiahao Wang, Shen Ye, Shiqi Zhang, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents a 45V high-precision current-feedback instrumentation amplifier (CFIA) that combines both chopping and auto-zeroing (AZ) to achieve 1.8- $mu $ V input offset (10 samples) and 33.5- $mu $ V input-referred ripple. The AZ is duty cycled to minimize power and silicon area, with a parallel auxiliary path operating during AZ …

Published in: IEEE Solid-State Circuits Letters
Page(s): 173 – 176
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3576393
Publisher: IEEE

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