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A 194.6-TOPS/W Pipelined All Current Domain Mixed Signal Compute in Memory in 28nm CMOS

A 194.6-TOPS/W Pipelined All Current Domain Mixed Signal Compute in Memory in 28nm CMOS 150 150
Author(s): Saideep Cherukuri, N.V. Kidambi, W.C. Wang, I. Chakraborty, S. Zhang, L. Shamieh, J.B. Steinberg, S. Mukhopadhyay

Abstract:

Mixed-signal CIM faces bit-cell nonlinearity, poor linearity at high frequency, and throughput limits. We present a hybrid pipelined current-domain MS-CIM macro featuring Bit-Cell Matched Linearization Interface (BMLI) and Loop-unrolled SAR ADC fabricated in 28 nm CMOS. A 256×256 SRAM array with 8-bit inputs, 8-bit weights achieve 10.16 TOPS peak throughput, 194.59 TOPS/W compute …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697990
Publisher: IEEE

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A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2

A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2 150 150
Author(s): Marco Pasotti, Riccardo Zurla, J. J. Bertolini Agnoletto, Emanuela Calvetti, Alessio Antolini, Andrea Lico, Giuseppe Desoli, Riccardo Vignali, Luca Iannelli, Luigi Croce, Francesco Zavalloni, Eleonora Franchi Scarselli, Alessandro Cabrini

Abstract:

In-memory computing (IMC) hardware accelerators for deep neural networks (DNNs) require storing a massive number of coefficients within a single computing macro to avoid performance degradation in multicore clusters. This aspect, often overlooked by common figures of merit (FoMs), can be effectively addressed by phase-change memory (PCM) technology, thanks to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3693894
Publisher: IEEE

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