Cells (biology)

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A Practical MRAM Logic-in-Memory Platform with Reference-Bitline Structure

A Practical MRAM Logic-in-Memory Platform with Reference-Bitline Structure 150 150
Author(s): Seongmin Ahn, Minjun Jang, Mingu Han, Bayartulga Ishdorj, Siyeol Lee, Taehui Na

Abstract:

The memory wall due to data movement is a major challenge that limits performance and energy efficiency in bitwise-operation-intensive applications. To address this issue, this paper proposes a global merged reference-based magnetic random-access memory (MRAM) logic-in-memory structure. The proposed structure generates operation-specific reference resistances by controlling the effective parallelism of …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3729230
Publisher: IEEE

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Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile One-Bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference

Sensing- and Periphery-Aware Modeling of a Hybrid MTJ–CMOS Nonvolatile One-Bit Sign-Weight Memory Subsystem for Energy-Constrained Edge Inference 150 150
Author(s): Byeong-Gwon Kim, Byeong-Kwon Ju, Ki-Young Lee

Abstract:

Spin-transfer-torque magnetic random-access memory (STT-MRAM) is attractive for nonvolatile one-bit sign-weight storage, but a favorable cell or local-read metric does not establish subsystem efficiency. We analyze a hybrid magnetic tunnel junction (MTJ)–complementary metal-oxide-semiconductor (CMOS) memory subsystem in which MTJs store static signs while sensing, reference generation, sign staging, scale …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3726699
Publisher: IEEE

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A Current-Mode Non-Destructive Circuit Readout Scheme for High-Density 3D Ferroelectric Memory

A Current-Mode Non-Destructive Circuit Readout Scheme for High-Density 3D Ferroelectric Memory 150 150
Author(s): CHaohan Wang, Wagdy Hussein, Yang Xiang, Shankha Mukherjee, Ismail Cevik, Fernando García-Redondo, Annachiara Spagnolo, Hyungrock Oh, Marie Garcia Bardon, Nick Van Helleputte, Julien Ryckaert, Geert Hellings, Dwaipayan Biswas, Jan Van Houdt

Abstract:

The AI era is demanding ever-increasing memory capacity and bandwidth, where 3D-stacked ferroelectric memory (FeRAMs) utilizing nondestructive readout (NDRO) ferroelectric capacitors (FeCAPs) stand as a promising candidate. This work addresses NDRO sensing signal challenges in deeply scaled 3D FeRAMs using a current-mode sensing scheme, co-designed with the device architecture to …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3727137
Publisher: IEEE

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Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM

Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM 150 150
Author(s): Kiseok Lee, Seongkwang Lim, Suman Datta, Shimeng Yu

Abstract:

Processing-in-memory (PIM) by implementing Boolean logic functions in dynamic random access memory (DRAM) has been proposed to alleviate the memory wall problem in data-intensive computing. However, quantitatively evaluating DRAM-based logic operations across different DRAM architectures remains challenging due to the lack of publicly available DRAM cell and peripheral transistor models …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 144 – 152
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704508
Publisher: IEEE

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Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM

Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM 150 150
Author(s): Yutian Zhang, Jiaquan Fang, Khawar Sarfraz, Mansun Chan

Abstract:

This work shows that a multitier complementary FET (CFET) static random access memory (SRAM) can decouple the area term from PPA-oriented transistor sizing. A topology-aware layout design is used to construct orthogonal and point-symmetric multitier CFET SRAM cells under 1-nm-class design rules, enabling high-density (HD), high-performance (HP), and high-current (HC) …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 159 – 166
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3709007
Publisher: IEEE

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CTH-CAM: A Cryogenic eDRAM-Based CAM With 1–26 Tunable Hamming Distance

CTH-CAM: A Cryogenic eDRAM-Based CAM With 1–26 Tunable Hamming Distance 150 150
Author(s): Jincheng Wang, Yuxin Zhou, Bin Ning, Lintao Lan, Yifei Li, Xufeng Kou, Yuhao Shu, Yajun Ha

Abstract:

Cryogenic approximate content-addressable memory (ACAM) offers an appealing solution that allows mismatches between the query and the stored data, measured by the Hamming distance (HD). However, in ACAM designs, increasing the word length shrinks the matchline (ML) voltage spacing between adjacent HD tolerance levels, thereby limiting the tunable-HD tolerance range …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3722705
Publisher: IEEE

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A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2

A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2 150 150
Author(s): Marco Pasotti, Riccardo Zurla, J. J. Bertolini Agnoletto, Emanuela Calvetti, Alessio Antolini, Andrea Lico, Giuseppe Desoli, Riccardo Vignali, Luca Iannelli, Luigi Croce, Francesco Zavalloni, Eleonora Franchi Scarselli, Alessandro Cabrini

Abstract:

In-memory computing (IMC) hardware accelerators for deep neural networks (DNNs) require storing a massive number of coefficients within a single computing macro to avoid performance degradation in multicore clusters. This aspect, often overlooked by common figures of merit (FoMs), can be effectively addressed by phase-change memory (PCM) technology, thanks to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 3193 – 3207
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3693894
Publisher: IEEE

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A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI

A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI 150 150
Author(s): Jiho Chun, Byeongseon Choi, Edward Jongyoon Choi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je

Abstract:

Computing in memory (CIM) has emerged as a promising architecture that can significantly reduce power consumption and latency in edge artificial intelligence (AI) devices. For battery-constrained edge devices, non-volatile memories (NVMs) are ideal due to their ability to retain neural network parameters even when powered down, ensuring rapid response time …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3717139
Publisher: IEEE

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Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS

Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS 150 150
Author(s): Jaeyong Jang, Mingu Han, Jaehwan Kim, Taehui Na

Abstract:

This article proposes an offset-canceling (OC) discharge-based sensing circuit (OCDC) for spin-transfer-torque magnetic random access memory (STT-MRAM). The proposed circuit simultaneously implements a merged reference line (MRL) architecture and threshold voltage ( $\mathbf {V}_{\mathbf {TH}}$ ) mismatch cancellation, resolving the structural incompatibility between the conventional OC schemes and MRL. A diode-connection-based, …

Published in: IEEE Solid-State Circuits Letters
Page(s): 210 – 213
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3715234
Publisher: IEEE

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