Capacitance

A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC With Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration

A 4-GS/s 53.5-dB SNDR 12.9 fJ/conv. TI-SAR ADC With Capacitive Nonlinearity Compensation and Dual-Mode Offset Calibration 150 150

Abstract:

Successive approximation register (SAR) analog-to-digital converters (ADCs) often employ dual-mode dynamic comparators to achieve both high speed and low noise. However, under low-supply operation, offset drift from mode transitions and degraded front-end linearity due to limited signal headroom become critical challenges. To address these issues, an adaptive current-injection scheme suppresses …

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An 11.5-Gb/s/pin, 0.4-V Driver-Supply Transmitter With Switched-Coupling Charge-Pump-Based Crosstalk Cancellation for Ultra-Dense Capacitively Coupled Channels

An 11.5-Gb/s/pin, 0.4-V Driver-Supply Transmitter With Switched-Coupling Charge-Pump-Based Crosstalk Cancellation for Ultra-Dense Capacitively Coupled Channels 150 150

Abstract:

This work presents an 11.5-Gb/s/pin transmitter (TX) for ultra-dense capacitively coupled channels that achieves near-complete eye-margin recovery while operating from a 0.4-V driver supply using a switched-coupling charge-pump-based crosstalk cancellation (SCCP-XTC) scheme. In the proposed scheme, one of four precharged capacitor banks in each XT cancellation (XTC) path …

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A W-Band Active Bidirectional Phase Shifter With 2° RMS Phase Error Over 26.4% FBW Using Back-Gate Biasing in 28-nm FD-SOI CMOS

A W-Band Active Bidirectional Phase Shifter With 2° RMS Phase Error Over 26.4% FBW Using Back-Gate Biasing in 28-nm FD-SOI CMOS 150 150

Abstract:

This article presents a W-band active bidirectional vector-sum phase shifter (Bi-VSPS) using a bidirectional phase-inverting variable-gain amplifier (Bi-PIVGA) with back-gate biasing in 28-nm fully depleted silicon-on-insulator (FD-SOI) CMOS. The Bi-PIVGA employs a neutralization technique that cancels the gate-to-drain capacitances of both active and inactive transistors in each signal direction. By …

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A MEMS-Free 4096-Pixel CMOS E-Nose Array With MOF-Based Molecular Selectivity, In-Pixel Thermal Regeneration, and a Compact Single-Coefficient Bandpass Sigma–Delta ADC

A MEMS-Free 4096-Pixel CMOS E-Nose Array With MOF-Based Molecular Selectivity, In-Pixel Thermal Regeneration, and a Compact Single-Coefficient Bandpass Sigma–Delta ADC 150 150

Abstract:

This work presents a CMOS-only [micro-electromechanical systems (MEMS)-free] electronic nose (e-nose) for concurrent multi-gas-sensing applications. The proposed system integrates 4096 capacitance-to-digital converter (CDC) pixels, each implementing a compact bandpass sigma–delta ( $\Sigma \Delta $ ) ADC with a single feedback coefficient and no additional feedforward or feedback paths, achieving each pixel footprint …

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A 2–18 GHz High-Efficiency CMOS Nonuniform Distributed Power Amplifier With a Novel Reconfigurable Inductive Termination

A 2–18 GHz High-Efficiency CMOS Nonuniform Distributed Power Amplifier With a Novel Reconfigurable Inductive Termination 150 150

Abstract:

This article presents a 2–18 GHz high-efficiency CMOS nonuniform distributed power amplifier (NDPA) with a novel reconfigurable inductive termination technique for ultra-broadband efficiency enhancement. First, the inherent drawback of the degrading efficiency with growing frequency in a conventional non-reconfigurable NDPA architecture with multi-octave bandwidth is studied. A simple and effective reconfigurable …

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A 7056-PPI Pixel Circuit With Low-Leakage Structure for Active-Matrix Monochrome Micro-LED Displays

A 7056-PPI Pixel Circuit With Low-Leakage Structure for Active-Matrix Monochrome Micro-LED Displays 150 150

Abstract:

This work presents a 5T2C pixel circuit for active-matrix (AM) micro-displays in near-eye display applications. The circuit supports monochrome micro light-emitting diode (micro-LED) displays with ultrahigh resolution of 7056 pixels per inch (PPI). The circuit is designed and fabricated based on medium-voltage (MV) devices from the 55-nm high-voltage (HV) CMOS …

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A 475-nW Area-Efficient Programmable Analog Feature Extraction Filterbank for Audio Classification

A 475-nW Area-Efficient Programmable Analog Feature Extraction Filterbank for Audio Classification 150 150

Abstract:

Audio classification in edge devices has many applications and can be implemented at varying levels of complexity, typically consisting of a feature extractor followed by a classifier. Such devices are often always-on, constantly listening to their surroundings, and have a small form factor; therefore, they require low-power operation and high …

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A Low-Voltage-CMOS AC–DC Converter With Series-Capacitor Pre-Regulation and Fine-Grained Capacitance Reallocation for Mains-Powered IoT

A Low-Voltage-CMOS AC–DC Converter With Series-Capacitor Pre-Regulation and Fine-Grained Capacitance Reallocation for Mains-Powered IoT 150 150

Abstract:

This article presents a power- and area-efficient switched-capacitor (SC) ac–dc converter in low-voltage (LV) CMOS for mains-powered Internet of Things (IoT) applications. The proposed converter adopts a single-stage series-capacitor architecture with fine-grained pre-rectification regulation, eliminating the need for intermediate high-voltage (HV) dc capacitors or HV dc–dc stages, thereby …

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Dual-Band Voltage-Controlled Oscillator for CB and HF RFID Bands in a Flexible IGZO Technology

Dual-Band Voltage-Controlled Oscillator for CB and HF RFID Bands in a Flexible IGZO Technology 150 150

Abstract:

In this work, a cross-coupled voltage-controlled oscillator (VCO) for the high frequency RFID and citizen bands (CBs) is investigated, and implemented on a flexible Indium gallium zinc oxide thin film transistor (TFT) technology. To circumvent the challenges of integrating passive components in this frequency range and minimize the circuit’s …

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