Buck converters

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A Three-Level Dual-Path Hybrid Buck Converter With Mitigated Capacitive Current and Seamless DVS Across a Wide Output Voltage Range

A Three-Level Dual-Path Hybrid Buck Converter With Mitigated Capacitive Current and Seamless DVS Across a Wide Output Voltage Range 150 150
Author(s): Jae-Hyun Kim, Jun-Gi Lee, Hyunki Han, Hyun-Sik Kim

Abstract:

This article presents a three-level dual-path (TLDP) buck converter tailored for mobile application processors (APs) with a 1.8-V input and 0.4–1.5-V output range. Conventional buck (CB) and multi-level buck (MLB) converters suffer from prohibitive DC resistance ( $R_{\mathrm {DCR}}$ ) losses in compact inductors as load current increases. Although various multi-path …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3710310
Publisher: IEEE

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A Zero-Voltage Switching Buck Converter With Enhanced Efficiency Over a Wide Load Range

A Zero-Voltage Switching Buck Converter With Enhanced Efficiency Over a Wide Load Range 150 150
Author(s): Jingyi Yuan, Qingqing Min, Siyang Liu, Lin Cheng

Abstract:

This article presents a wide-input-range buck converter featuring a conduction-loss-minimized zero-voltage switching (ZVS) technique. The proposed ZVS topology enables accurate ZVS operation across a wide range of input voltage ( $V_{\mathrm {IN}}$ ) and load current ( $I_{\mathrm {O}}$ ). By keeping the auxiliary inductor current pulse in the ZVS branch separate …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3609411
Publisher: IEEE

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Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency

Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency 150 150
Author(s): Yichen Xu, Zhaoqing Wang, Rentao Wan, Suhwan Kim, Minxiang Gong, Ram Krishnamurthy, Xin Zhang, Mingoo Seok

Abstract:

This paper proposes a digital low-dropout regulator (DLDO)-assisted buck converter featuring one-step computational droop compensation and DLDO feedback-controlled current handover. The 28-nm test chip achieves a 68-mV droop voltage and a 112-ns settling time for a 1A/0.8ns load step while maintaining a high peak efficiency of 95.5%.

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3581844
Publisher: IEEE

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