Bit error rate

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An Antenna-to-Bits F-Band 120-Gbps CMOS RF-64QAM Receiver

An Antenna-to-Bits F-Band 120-Gbps CMOS RF-64QAM Receiver 150 150
Author(s): Youssef O. Hassan, Mohammad Oveisi, Zisong Wang, Payam Heydari

Abstract:

A CMOS 100–140-GHz end-to-end receiver (RX) is presented that integrates the antenna input all the way to the bitstream output, while demodulating 64QAM/16QAM/QPSK entirely in the analog domain. A sequential asynchronous demodulation method enables 120-Gbps operation at a notably small baseband power consumption. Fabricated in a 22-nm FDSOI …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3648748
Publisher: IEEE

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High-Entropy Analog-Based Strong Physical Unclonable Function With Area-to-Entropy-ratio of 166 F2/bit

High-Entropy Analog-Based Strong Physical Unclonable Function With Area-to-Entropy-ratio of 166 F2/bit 150 150
Author(s): Alessandro Catania, Sebastiano Strangio, Maksym Paliy, Christian Sbrana, Michele Bertozzi, Giuseppe Iannaccone

Abstract:

In this letter, we present a high-entropy strong physically unclonable function (PUF) utilizing weak-inversion current mirrors implemented in a standard 65-nm CMOS technology. Each response bit of the proposed PUF relies on the threshold voltage differences of minimum-sized transistors arranged in a $32\times 32$ matrix. The analog operating principle enables encoding …

Published in: IEEE Solid-State Circuits Letters
Page(s): 309 – 312
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3616263
Publisher: IEEE

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A 48-Gb/s Inductorless PAM-4 Optical Receiver With 1.28-pJ/bit Efficiency in 28-nm CMOS

A 48-Gb/s Inductorless PAM-4 Optical Receiver With 1.28-pJ/bit Efficiency in 28-nm CMOS 150 150
Author(s): Chongyun Zhang, Li Wang, Fuzhan Chen, Quan Pan, Xianbo Li, C. Patrick Yue

Abstract:

This work presents a 48-Gb/s four-level pulse amplitude modulation (PAM-4) optical receiver (ORX) with a linear analog front-end (AFE) and an integrated sampler. The AFE employs a transadmittance-stage transimpedance-stage (TAS-TIS) topology, replacing conventional CML-based variable gain amplifiers (VGAs) and post-amplifiers, avoiding continuous-time linear equalizers and passive inductors while preserving …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3607107
Publisher: IEEE

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