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A High-Density Low-Leakage and Low-Power Fully Voltage-Stacked SRAM for IoT Application

A High-Density Low-Leakage and Low-Power Fully Voltage-Stacked SRAM for IoT Application 150 150
Author(s): Sekeon Kim, Giseok Kim, Kyeongrim Baek, Keonhee Cho, Hyunjun Kim, Yeonho Jung, Dongwook Seo, Sangyeop Baeck, Sungjae Lee, Seong-Ook Jung

Abstract:

The general approach to suppress leakage in static random access memory (SRAM) is to use a low voltage ( $V_{text {L}}$ ), generated by a low-dropout regulator (LDO), as the cell supply voltage (CVDD) of SRAM array in the standby mode. However, the effectiveness of lowering CVDD is constrained by the …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3582974
Publisher: IEEE

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Cryogenic Hyperdimensional In-Memory Computing Using Ferroelectric TCAM

Cryogenic Hyperdimensional In-Memory Computing Using Ferroelectric TCAM 150 150
Author(s): Shivendra Singh Parihar, Shubham Kumar, Swetaki Chatterjee, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch

Abstract:

Cryogenic operations of electronics present a significant step forward to achieve huge demand of in-memory computing (IMC) for high-performance computing, quantum computing, and military applications. Ferroelectric (FE) is a promising candidate to develop the complementary metal oxide semiconductor (CMOS)-compatible nonvolatile memories. Hence, in this work, we investigate the effectiveness …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 34 – 41
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3547797
Publisher: IEEE

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Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W

Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W 150 150
Author(s): Yusaku Shiotsu, Satoshi Sugahara

Abstract:

A binarized neural-network (BNN) accelerator macro is developed based on a processing-in-memory (PIM) architecture having the ability of eight-parallel multiply-accumulate (MAC) processing. The parallel-processing PIM macro, referred to as a PPIM macro, is designed to perform the parallel processing with no use of multiport SRAM cells and to achieve the …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 25 – 33
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3538702
Publisher: IEEE

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