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Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS

Merged-Reference-Compatible Offset-Canceling Discharge-Based Sensing Circuit for STT-MRAM in 28-nm CMOS 150 150
Author(s): Jaeyong Jang, Mingu Han, Jaehwan Kim, Taehui Na

Abstract:

This article proposes an offset-canceling (OC) discharge-based sensing circuit (OCDC) for spin-transfer-torque magnetic random access memory (STT-MRAM). The proposed circuit simultaneously implements a merged reference line (MRL) architecture and threshold voltage ( $\mathbf {V}_{\mathbf {TH}}$ ) mismatch cancellation, resolving the structural incompatibility between the conventional OC schemes and MRL. A diode-connection-based, …

Published in: IEEE Solid-State Circuits Letters
Page(s): 210 – 213
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3715234
Publisher: IEEE

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A Low-Power MRAM-Based Nonvolatile Flip-Flop Architecture for Register and System Applications

A Low-Power MRAM-Based Nonvolatile Flip-Flop Architecture for Register and System Applications 150 150
Author(s): Bayartulga Ishdorj, Taehui Na

Abstract:

This work presents a minimal nonvolatile flip-flop (NVFF) hybrid architecture and an NV static contention-free differential FF (nvSCDFF) cell that reduces the overhead associated with replicated NV circuitry in conventional in situ NVFFs while enabling low power. By using only one NVFF per column and compact SCDFF-based volatile flip-flops (FFs), …

Published in: IEEE Solid-State Circuits Letters
Page(s): 206 – 209
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3713204
Publisher: IEEE

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Open DRAM Model—Part I: Cross-Layer Device, Array, and Circuit Analysis With BL-to-BL Coupling Mitigation for 4F2 VCT DRAM

Open DRAM Model—Part I: Cross-Layer Device, Array, and Circuit Analysis With BL-to-BL Coupling Mitigation for 4F2 VCT DRAM 150 150
Author(s): Kiseok Lee, Seongkwang Lim, Suman Datta, Shimeng Yu

Abstract:

Dynamic random access memory (DRAM) scaling toward 4F2 vertical channel transistors (VCTs) fundamentally reshapes device, array, and circuit-level design tradeoffs. However, the lack of an open-source DRAM device model that is calibrated with recent industry trends prohibits broader innovations in the research community. In this work, we present an “Open …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 135 – 143
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704358
Publisher: IEEE

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Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM

Open DRAM Model—Part II: Enabling Processing-in-Memory in 3-D DRAM 150 150
Author(s): Kiseok Lee, Seongkwang Lim, Suman Datta, Shimeng Yu

Abstract:

Processing-in-memory (PIM) by implementing Boolean logic functions in dynamic random access memory (DRAM) has been proposed to alleviate the memory wall problem in data-intensive computing. However, quantitatively evaluating DRAM-based logic operations across different DRAM architectures remains challenging due to the lack of publicly available DRAM cell and peripheral transistor models …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 144 – 152
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3704508
Publisher: IEEE

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A3D-MoE: Acceleration of Large Language Models With Mixture of Experts via 3-D Heterogeneous Integration

A3D-MoE: Acceleration of Large Language Models With Mixture of Experts via 3-D Heterogeneous Integration 150 150
Author(s): Wei-Hsing Huang, Janak Sharda, Cheng-Jhih Shih, Yuyao Kong, Faaiq Waqar, Pin-Jun Chen, Yingyan Lin, Shimeng Yu

Abstract:

Conventional large language models (LLMs) have large parameter sets, making inference costly and energy-intensive; mixture-of-experts (MoEs) mitigates this by activating fewer weights per token, but fine-grained MoE LLMs still face runtime workload variability, inefficient conventional scheduling, and high bandwidth memory (HBM) loading energy/bandwidth demands. A3D-MoE addresses these with 3…

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 176 – 184
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3713957
Publisher: IEEE

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Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM

Topology-Aware Layout Design for Area-Decoupled Transistor Sizing in Multitier CFET SRAM 150 150
Author(s): Yutian Zhang, Jiaquan Fang, Khawar Sarfraz, Mansun Chan

Abstract:

This work shows that a multitier complementary FET (CFET) static random access memory (SRAM) can decouple the area term from PPA-oriented transistor sizing. A topology-aware layout design is used to construct orthogonal and point-symmetric multitier CFET SRAM cells under 1-nm-class design rules, enabling high-density (HD), high-performance (HP), and high-current (HC) …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 159 – 166
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3709007
Publisher: IEEE

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A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2

A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 × 512-Weight Layers and 28M Weights×TOPs/W/mm2 150 150
Author(s): Marco Pasotti, Riccardo Zurla, J. J. Bertolini Agnoletto, Emanuela Calvetti, Alessio Antolini, Andrea Lico, Giuseppe Desoli, Riccardo Vignali, Luca Iannelli, Luigi Croce, Francesco Zavalloni, Eleonora Franchi Scarselli, Alessandro Cabrini

Abstract:

In-memory computing (IMC) hardware accelerators for deep neural networks (DNNs) require storing a massive number of coefficients within a single computing macro to avoid performance degradation in multicore clusters. This aspect, often overlooked by common figures of merit (FoMs), can be effectively addressed by phase-change memory (PCM) technology, thanks to …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 3193 – 3207
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3693894
Publisher: IEEE

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A 0.68nJ/solution Inverse-Matrix-Vector Multiplication Solver with Decoupled Input Injection Scheme in 65nm CMOS

A 0.68nJ/solution Inverse-Matrix-Vector Multiplication Solver with Decoupled Input Injection Scheme in 65nm CMOS 150 150
Author(s): Hsiang-Chun Cheng, Mayank Palaria, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen

Abstract:

This paper presents an analog inverse-matrix-vector multiplication (IMVM) solver that addresses the input loading limitation of prior crossbar-based implementations. The proposed decoupled input injection scheme isolates the input circuit from the crossbar array, enabling the use of smaller crossbar conductance for lower power consumption and relaxing the required op amp …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3717659
Publisher: IEEE

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Raisu: A Radiation-Tolerant Neuromorphic Imager With In-Pixel Self-Healing and Unified Spiking Processing for Spaceborne Vision

Raisu: A Radiation-Tolerant Neuromorphic Imager With In-Pixel Self-Healing and Unified Spiking Processing for Spaceborne Vision 150 150
Author(s): Quan Cheng, Qiufeng Li, Zhengke Yang, Zhen Kong, Gaoqiang Niu, Yuan Liang, Jiamin Li, Jeong Hoan Park, Wang Liao, Hiromitsu Awano, Takashi Sato, Longyang Lin, Masanori Hashimoto

Abstract:

Spaceborne imaging systems operate under severe radiation and energy constraints, where single-event effects (SEEs), total ionizing dose (TID), and displacement damage dose (DDD) critically degrade reliability and performance. This work presents a radiation-tolerant neuromorphic imager prototype featuring a fully spike-based neuromorphic vision architecture with in-pixel self-healing capability and an integrated …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715724
Publisher: IEEE

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