Architecture

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A Runtime Reconfigurable Array (RTRA) for Multiprogram ML and DSP Acceleration With Hierarchical Partitioning and On-Chip Multilevel Scheduling

A Runtime Reconfigurable Array (RTRA) for Multiprogram ML and DSP Acceleration With Hierarchical Partitioning and On-Chip Multilevel Scheduling 150 150
Author(s): Hongseok Lee, Jack Burd, Tim Ling, Yao-Kai Yang, Nian-Shyang Chang, Wen-Ching Chen, Chi-Shi Chen, Tzi-Dar Chiueh, Michael Kuan-Tse Lee, Chia-Hsiang Yang, Dejan Marković

Abstract:

Emerging applications with highly dynamic digital signal processing (DSP) and machine-learning (ML) workloads demand a hardware platforms that simultaneously deliver high performance, high energy efficiency, and low-latency reconfiguration. Such systems must adapt to evolving algorithms, variable data rates, and multiprogram tenancy without incurring prohibitive switching overhead. The conventional reconfigurable architectures …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5296 – 5312
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715500
Publisher: IEEE

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A 28nm Reconfigurable CAM for High-Utilization String Matching

A 28nm Reconfigurable CAM for High-Utilization String Matching 150 150
Author(s): Zhiting Lin, Lixin Zheng, Yang Lou, Qiushi Feng, Baofa Wu, Jiajun Long, Xianluan Zhao, Mingyu Peng, Juntao Ge, Chenglong Duan, Yu Liu, Xin Li, Xiulong Wu

Abstract:

Content-addressable memory (CAM) is essential for data-intensive applications such as network packet classification, but conventional row-by-row architectures store one fixed-width rule per row, so variable-length rules must be padded to the row width, limiting the average array utilization to 53.1% for a representative uniform 1–16-byte rule-length distribution. This letter proposes a …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3743206
Publisher: IEEE

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Algorithm–Architecture Co-Design for Vertically Integrated AI and HPC Systems: Challenges, Advantages, and Future Outlook

Algorithm–Architecture Co-Design for Vertically Integrated AI and HPC Systems: Challenges, Advantages, and Future Outlook 150 150
Author(s): Patricia Gonzalez-Guerrero, Aaron R. Young, Giuseppe Di Guglielmo, Benjamin Parpillon, Narasinga Rao Miniskar, Nikhil Kumar Cherukuri, Abhay Nayak, Meriam Gay Bautista-Jurney, Mario Vega, George Michelogiannakis, Thom Popovici, Yu Cao, Jeffrey S. Vetter, John Shalf, Farah Fahim

Abstract:

Next-generation scientific instruments in high-energy physics, X-ray imaging, fusion diagnostics, and other data-intensive applications generate data rates that increasingly exceed practical communication bandwidth and power budgets, making the traditional approach of transferring raw data to remote computing systems unsustainable. This paper presents the Vertically Integrated AI for Sensing and High-Performance …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3742652
Publisher: IEEE

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Design Techniques for 48/56 Gb/s/Lane UCIe-S D2D and 45 Gb/s/Lane UCIe-Like Off-Package Links

Design Techniques for 48/56 Gb/s/Lane UCIe-S D2D and 45 Gb/s/Lane UCIe-Like Off-Package Links 150 150
Author(s): Susnata Mondal, Sashank Krishnamurthy, Shuhei Yamada, Zhaokai Liu, Junyi Qiu, Soumya Bose, Zuoguo Wu, Gerald Pasdast, James Jaussi, Mozhgan Mansuri

Abstract:

This article presents a Universal Chiplet Interconnect Express (UCIe)-compliant die-to-die (D2D) transceiver PHY for chiplet interconnects over a standard organic package, along with an extension to off-package interconnects over printed circuit board (PCB) channels. The transceiver introduces several power-efficient, high-performance techniques, including an impedance-invariant passive continuous-time linear equalizer (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3737168
Publisher: IEEE

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QEPC: Deferred-Evaluation Probabilistic Computing for Wearable AI — Architecture, Simulation Study, and Design Limits

QEPC: Deferred-Evaluation Probabilistic Computing for Wearable AI — Architecture, Simulation Study, and Design Limits 150 150
Author(s): Mohan Raj Manoharan

Abstract:

Wearable AI workloads such as sensor fusion, physiological inference and uncertainty quantification are probabilistic, yet the neural processing units that serve them are deterministic matrix-multiply engines that discard distributional information at every layer. We describe QEPC, a deferred-evaluation execution model in which probability mass functions are maintained in non-volatile state …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3740368
Publisher: IEEE

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A Modeling/Rendering Unified 3DGS Processor Based on Locality-Optimized Computation and Reconfigurable Architecture

A Modeling/Rendering Unified 3DGS Processor Based on Locality-Optimized Computation and Reconfigurable Architecture 150 150
Author(s): Xiaoyu Feng, Hedi Wang, Songran Xiao, Huazhong Yang, Yongpan Liu

Abstract:

Traditional 3-D Gaussian-splatting (3DGS) modeling relies on iterative optimization, leading to substantial latency and limited generalizability. Feedforward 3DGS alleviates these limitations by generating Gaussians through a single network inference. However, most existing processors are optimized for optimization-based 3DGS and do not fully exploit the distinct computational characteristics of feedforward 3DGS. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3737807
Publisher: IEEE

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3D-Integrated Near-Sensor AI for Energy-Constrained Environmental Monitoring Systems

3D-Integrated Near-Sensor AI for Energy-Constrained Environmental Monitoring Systems 150 150
Author(s): Arya Upadhyay

Abstract:

Moving sensor data and neural-network operands through conventional external-memory hierarchies can constitute a substantial fraction of the energy required for edge inference. Motivated by a three-tier near-sensor organization, this work evaluates memory localization using a controlled architecture-level study and an independent transistor-level communication-link analysis. Five convolution configurations are evaluated on …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3735890
Publisher: IEEE

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A Fully Integrated Wireless Multimodal Biosensing System-on-Chip for Stress Monitoring

A Fully Integrated Wireless Multimodal Biosensing System-on-Chip for Stress Monitoring 150 150
Author(s): Min-Hua Chang, Lin Chou, Yen-Jen Liu, Chen-Hsing Hsu, Ying-Yu Yang, Bo-Cheng Juan, Guan-Yu Lin, Yi-Jie Lin, Yao-Wei Huang, An-Ting Teng, Chun-Wei Chiu, Yi-Chen Hsiao, Yen-Yu Chen, Nitish Kumar, Shu-Ping Lin, Yu-Te Liao

Abstract:

A fully integrated multimodal biosensing system-on-chip (SoC) for stress monitoring is presented. The proposed SoC integrates electrocardiography (ECG), electrochemical (ECH), photoplethysmography (PPG), and galvanic skin response (GSR) sensing together with an on-chip transmitter (TX), wake-up receiver (WuRX), and power-management unit (PMU) for compact, standalone operation. ECG and ECH share a …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3729275
Publisher: IEEE

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An 8K-Spin Ising Machine IC With Reconfigurable Many-Body Spin Interactions and 1-D Multi-Chip Scalability

An 8K-Spin Ising Machine IC With Reconfigurable Many-Body Spin Interactions and 1-D Multi-Chip Scalability 150 150
Author(s): Jaeyeong Kim, Jae-Yoon Sim

Abstract:

Combinatorial optimization problems (COPs) have attracted growing interest in CMOS Ising machines as hardware accelerators for near-optimal solution search. However, practical large-scale COP solving remains challenging because existing CMOS Ising machines face substantial preprocessing overhead for irregular or higher order problems and are limited in scalability beyond a single chip. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3730399
Publisher: IEEE

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