Antennas

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A 100+Gb/s 252–283-GHz RF-Amplifier-Integrated TX/RX Chipset in Standard 65-nm Bulk CMOS

A 100+Gb/s 252–283-GHz RF-Amplifier-Integrated TX/RX Chipset in Standard 65-nm Bulk CMOS 150 150
Author(s): Zhicheng Lin, Hiu Lok Tam, Hao Guo, Xiaoyue Xia, Zijun Guo, Kam Man Shum, Pui-In Mak, Chi Hou Chan

Abstract:

This article presents a 252–283-GHz amplifier-last transmitter (TX) and amplifier-first receiver (RX) wireless front end in standard 65-nm bulk CMOS technology, targeting IEEE 802.15.3d/802.15.3-compliant high-speed point-to-point wireless communications. To overcome the challenges of limited transistor gain and high passive loss that often limit the implementation of J-band RF amplifiers, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3730962
Publisher: IEEE

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A Thermally Adaptive Ku-Band Array-Scalable Transmitter Incorporating VSWR-Resilient PA for Ground Terminal Phased-Array Applications

A Thermally Adaptive Ku-Band Array-Scalable Transmitter Incorporating VSWR-Resilient PA for Ground Terminal Phased-Array Applications 150 150
Author(s): Mohamed Eleraky, Alessandro Novello, Giorgio Cristiano, Basem Abdelaziz Abdelmagid, Yuqi Liu, Jianping Zeng, Jinglong Xu, Boce Lin, Jonas Nann, Hangxing Liu, Marco Saif, Niccolò Villaggi, Lavinia Recchioni, Tzu-Yuan Huang, Thomas Burger, Thomas Kleier, Hua Wang

Abstract:

This article presents an eight-channel dual-polarized Ku-band transmitter (Tx) beamformer integrated circuit (BFIC) fabricated in a 22-nm GlobalFoundries FDSOI process. Each channel integrates independent phase and gain control utilizing a 7-bit active phase shifter (PS) and a 5.5-bit attenuator (ATT). To mitigate performance degradation caused by load impedance variations in …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 19
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3727539
Publisher: IEEE

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An IEEE802.15.4a/z/ab Compatible IR-UWB 2TRX With Full-Duplex Radar Sensing and Aliasing Suppressing Semisynchronous TX

An IEEE802.15.4a/z/ab Compatible IR-UWB 2TRX With Full-Duplex Radar Sensing and Aliasing Suppressing Semisynchronous TX 150 150
Author(s): Anoop Narayan Bhat, Erwin Allebes, Elbert Bechthum, Zule Xu, Stan van der Ven, Mohieddine El Soussi, Johan van Den Heuvel, Paul van Zeijl, Paul Mateman, Murat Eskiyerli, Stefano Traferro, Amirashkan Farsaei, Evgenii Tiurin, Sahan Gamage, Pepijn Boer, Igor Petrov, Jochem Govers, Huib Visser, Martijn Hijdra, Sharada Prasad Shantharam, Ivo Marques, Gururaja Kasanadi Ramachandra, Kaijie Ding, Ran Li, Aasish Boora, Peter Vis, Mario Konijnenburg, Arjan Breeschoten, Peng Zhang, Yao-Hong Liu, Christian Bachmann

Abstract:

This letter presents an 802.15.4ab/a/z compatible IR-UWB 2TRX highlighting a full-duplex-based radar, a semisynchronous TX and TRX’s digital baseband. A capacitive tuning technique proposed in the electrical balance duplexer (EBD)-based duplex RF front-end (RF-FE) improves TX-antenna insertion loss by 1.4 dB and the sensitivity of TX–RX …

Published in: IEEE Solid-State Circuits Letters
Page(s): 190 – 193
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3697493
Publisher: IEEE

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A 300-GHz 2-D Scalable 4 × 4 Phased-Array Receiver With Half-Wavelength Element Spacing in 65-nm CMOS

A 300-GHz 2-D Scalable 4 × 4 Phased-Array Receiver With Half-Wavelength Element Spacing in 65-nm CMOS 150 150
Author(s): Huanting Deng, Kaizhe Guo, Yihan Wang, Houyi Yan, Jiyao Wang, Mengru Yang, Jian Guo, Peng Gu, Xiaohu You, Dixian Zhao

Abstract:

This article presents a 300-GHz 2-D scalable $4\times 4$ phased-array receiver (RX) with half-wavelength element spacing in 65-nm CMOS. To achieve high scalability, a hybrid local oscillator (LO)–intermediate frequency (IF) beamforming scheme based on a coupled oscillator array is proposed, together with an area-efficient aperture-coupled antenna implemented on quartz. The …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3711687
Publisher: IEEE

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A 436–472 GHz 4-Element IF Beamforming Phased-Array Receiver in 65-nm CMOS

A 436–472 GHz 4-Element IF Beamforming Phased-Array Receiver in 65-nm CMOS 150 150
Author(s): Hao Guo, Hao-Tao Hu, Zhicheng Lin, Zijun Guo, Xiaoyue Xia, Kaizhe Guo, Kam Man Shum, Pui-In Mak, Chi Hou Chan

Abstract:

This article presents a 436–472GHz four-element intermediate-frequency (IF) beamforming phased-array receiver fabricated in 65-nm CMOS, targeting scalable terahertz (THz) phased-array systems. The proposed receiver adopts a two-step mixing scheme to reduce the area overhead of the IF beamforming implementation, thereby enhancing the array scalability at THz frequencies. Each receive channel …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3710258
Publisher: IEEE

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1-Transistor-Dynamic Random Access Memory as Reservoir for Temporal Signal Processing

1-Transistor-Dynamic Random Access Memory as Reservoir for Temporal Signal Processing 150 150
Author(s): Md Yasir Bashir, Lalith Adithya Sai C., Shubham Sahay

Abstract:

Reservoir computing (RC), a computational paradigm inspired by the recurrent neural networks (RNNs), offers a promising framework for efficient temporal processing with minimal training overhead. Hardware implementation of RC primitive requires devices that exhibit short-term memory, nonlinearity, and energy-efficient state-switching dynamics. While emerging nonvolatile memory (eNVM) technologies have been explored …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 120 – 128
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3690766
Publisher: IEEE

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Comparative Analysis of Sense Amplifier Circuits for Hybrid CMOS-MTJ CIM Architecture

Comparative Analysis of Sense Amplifier Circuits for Hybrid CMOS-MTJ CIM Architecture 150 150
Author(s): Yashvardhan Singh, Siddharth Penumatsa, Prashanth Barla

Abstract:

Spin-transfer torque magnetic tunnel junction (STT-MTJ) is widely recognized as a promising device for computation-in-memory (CIM) architecture due to its advantages, such as simple nonvolatile structure, CMOS compatibility, and scalability. In spite of the advantages, achieving reliable and efficient sensing of STT-MTJ remains a design challenge. This work presents a …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 95 – 103
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3690460
Publisher: IEEE

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A CMOS Probabilistic Computing Chip With Hardware-Aware Learning

A CMOS Probabilistic Computing Chip With Hardware-Aware Learning 150 150
Author(s): Jinesh Jhonsa, William Whitehead, Yihao Wu, David Mccarthy, Shuvro Chowdhury, Kerem Y. Camsari, Luke Theogarajan

Abstract:

This work demonstrates a compact probabilistic computing system based on a physics-inspired probabilistic bit (p-bit) architecture with 440 interacting spins configured in a chimera graph and occupying 0.44 mm2 of silicon area. Area efficiency is achieved through a current-mode neuron update circuit and a mixed-signal design approach that integrates pitch-matched standard-cell analog …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 86 – 94
Year of Publication: 2026
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2026.3689506
Publisher: IEEE

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A 138 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas Achieving Sub-1-pJ/b Efficiency in 28-nm Bulk CMOS

A 138 Gb/s D-Band 2-D Scalable Transceiver Array With On-Chip Antennas Achieving Sub-1-pJ/b Efficiency in 28-nm Bulk CMOS 150 150
Author(s): Hesham Beshary, Yikuan Chen, Ali M. Niknejad

Abstract:

This article presents a D-band 2-D scalable phased array that integrates a $2{\,}\times{\,} 2$ transceiving (TRX) radio frequency (RF) beamformer with on-chip antennas (OCAs) and a $\times 16$ local-oscillator (LO) multiplication chain. The 2-D array scalability is demonstrated by tiling $2{\,}\times{\,} 2$ chips into an array using a low-cost package to build a 16…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3704818
Publisher: IEEE

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