analog-front-end (AFE)

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A 77-dB DR Two-Stage SAR ADC for Low-Gain Analog Front-Ends Using Asynchronous Pipelining and RC Snubber Reference Stabilization

A 77-dB DR Two-Stage SAR ADC for Low-Gain Analog Front-Ends Using Asynchronous Pipelining and RC Snubber Reference Stabilization 150 150
Author(s): Jun Feng, Rares Bodnar, Roberto Maurino, Marcel J. M. Pelgrom, Filip Tavernier

Abstract:

The analog front-end (AFE) often bottlenecks the power of modern receiver chains, burdened by the large-signal linearity required before the ADC. This work introduces a 77-dB DR, 200-MS/s two-stage SAR ADC that can alleviate much of this burden by offering a significantly lower input-referred noise (IRN) to enable low-gain …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3686660
Publisher: IEEE

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A 760 mVPP-Input-Range, 103.6dB-SNDR Direct-Digitization Sensor Readout With Pseudo-Differential Integrator and Impedance-Equalized RDAC

A 760 mVPP-Input-Range, 103.6dB-SNDR Direct-Digitization Sensor Readout With Pseudo-Differential Integrator and Impedance-Equalized RDAC 150 150
Author(s): Kaiwen Zhou, Jianhong Zhou, Yijie Li, Yuying Li, Tian Dong, Zhiliang Hong, Jiawei Xu

Abstract:

A high-precision, direct-digitization sensor readout (DD-RO) based on a continuous-time delta-sigma modulator (CT- $\Delta \Sigma $ M) is presented. The proposed DD-RO incorporates several key innovations to enhance performance. First, a pseudo-differential current-balancing integrator (PD-CBI) significantly extends the linear input range, whereas its intrinsically limited common-mode input range and CMRR are …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3686843
Publisher: IEEE

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A Continuous-Time Zoom Sensor Readout Frontend With Fast Tracking and Floating-Gm-CCO Integrator

A Continuous-Time Zoom Sensor Readout Frontend With Fast Tracking and Floating-Gm-CCO Integrator 150 150
Author(s): Haoyang Luo, Zongnan Wang, Jiarui Wang, Bingrui Li, Zilong Shen, Yang Liu, Xiaojie Duan, Yuan Wang, Xiyuan Tang

Abstract:

Emerging edge applications processing weak signals in noisy environments demand sensor readout frontends with low noise, low power, high dynamic range (DR), and high input impedance. This article presents a zoom sensor readout frontend design that can track signals with rapid changes over a wide DR with high energy efficiency. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3677053
Publisher: IEEE

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A Bidirectional Neuromodulation Chipset With Algorithm-Aware AFE Optimization and High-Voltage-Compliant Stimulation

A Bidirectional Neuromodulation Chipset With Algorithm-Aware AFE Optimization and High-Voltage-Compliant Stimulation 150 150
Author(s): Xiaohua Huang, Hoda Yassin, Beatriz Lafuente Alcazar, Arash Akhoundi, Dante G. Muratore

Abstract:

This work presents a bidirectional neuromodulation chipset with 64-channel neural analog front-end (AFE), and a four-channel current stimulator. The chipset employs a heterogeneous architecture, combining a 28-nm low-voltage (LV) CMOS process for the AFE and the digital backend (DBE) to improve area and power efficiency, with a 180-nm high-voltage (HV) …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3650066
Publisher: IEEE

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A 112-Gb/s PAM4 Receiver With a Phase Equalization AFE in 7-nm FinFET

A 112-Gb/s PAM4 Receiver With a Phase Equalization AFE in 7-nm FinFET 150 150
Author(s): Huanan Guo, Yufeng Yao, Xiang Gao

Abstract:

To reduce the bit-error-rate (BER), equalizers are implemented in high-speed SerDes receivers (RX) to compensate for channel insertion loss and mitigate intersymbol interference (ISI). Conventional analog front-end (AFE) designs primarily focus on amplitude gain while neglecting the influence of phase shift. This brief presents a phase equalization (PEQ) AFE design …

Published in: IEEE Solid-State Circuits Letters
Page(s): 5 – 8
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3637833
Publisher: IEEE

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A 4.6 μW, 133-VPP Common-Mode Interference-Tolerant Biopotential Amplifier for Two-Electrode Recording System in 110-nm CMOS

A 4.6 μW, 133-VPP Common-Mode Interference-Tolerant Biopotential Amplifier for Two-Electrode Recording System in 110-nm CMOS 150 150
Author(s): Yongjae Park, Yeong-Jin Mo, Jeong-Hoon Kim, Gert Cauwenberghs, Seong-Jin Kim

Abstract:

This article presents a biopotential recording analog front-end (AFE) specifically tailored for a two-electrode measurement system, capable of capturing small biopotential signals while tolerating a large common-mode interference (CMI) over 130 VPP. By leveraging the Miller effect, the proposed CMI-Follower provides a significantly low common-mode input impedance ( $Z_{\text {IN-CM-C}}$ ), achieving …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3613410
Publisher: IEEE

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A 0.5-/0.95-dB NF, 50-/25-Ω Configurable CMOS Front-End ASIC for the Readout of Liquid Argon Calorimeter in the LHC

A 0.5-/0.95-dB NF, 50-/25-Ω Configurable CMOS Front-End ASIC for the Readout of Liquid Argon Calorimeter in the LHC 150 150
Author(s): Mietek Dabrowski, Filip Tavernier, Paul Leroux

Abstract:

This article presents the design of a four-channel front-end application specific integrated circuit (ASIC), ATLAS liquid argon front-end (ALFE), developed for the readout of the liquid-argon calorimeter (LAr) detector in the ATLAS experiment at the Large Hadron Collider (LHC). ALFE enables the readout of current signals induced in the LAr …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3602751
Publisher: IEEE

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A 48-Gb/s Inductorless PAM-4 Optical Receiver With 1.28-pJ/bit Efficiency in 28-nm CMOS

A 48-Gb/s Inductorless PAM-4 Optical Receiver With 1.28-pJ/bit Efficiency in 28-nm CMOS 150 150
Author(s): Chongyun Zhang, Li Wang, Fuzhan Chen, Quan Pan, Xianbo Li, C. Patrick Yue

Abstract:

This work presents a 48-Gb/s four-level pulse amplitude modulation (PAM-4) optical receiver (ORX) with a linear analog front-end (AFE) and an integrated sampler. The AFE employs a transadmittance-stage transimpedance-stage (TAS-TIS) topology, replacing conventional CML-based variable gain amplifiers (VGAs) and post-amplifiers, avoiding continuous-time linear equalizers and passive inductors while preserving …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3607107
Publisher: IEEE

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A 10.9nV/√Hz, 74.9dB-DR, 20MS/s Ultrasound Analog Front End for Fully-Digital Beamforming

A 10.9nV/√Hz, 74.9dB-DR, 20MS/s Ultrasound Analog Front End for Fully-Digital Beamforming 150 150
Author(s): Changde Ding, Yan Zhu, Pengjie Wang, Zhiliang Hong, Jiawei Xu

Abstract:

This letter presents a compact and energy-efficient analog front-end (AFE) circuit for fully-digital beamforming in endoscopic and catheter-based 3D-ultrasound imaging. The AFE converts single-ended analog input from each transducer element into a 10-bit digital output through a low-noise amplifier (LNA) and a 20 MS/s SAR ADC. To minimize chip area …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3581584
Publisher: IEEE

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