Amplifiers

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A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion

A 12-bit 1-GS/s SAR-Assisted Pipeline ADC With Gain-Stable Dual-Path Residue Amplification and Partially Look-Ahead Parallel Conversion 150 150
Author(s): Peng Wang, Yaning Wang, Fule Li, Zhihua Wang

Abstract:

This article presents a 12-bit, 1-GS/s SAR-assisted pipelined ADC implemented in 28-nm CMOS featuring accurate residue amplification (RA) with low gain variation. A dual-path residue amplifier embeds an open-loop gain-error-cancellation path within the closed-loop amplification path, providing accurate gain and robust gain stability without additional timing or power overhead. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5706 – 5719
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3713446
Publisher: IEEE

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A 14-bit 1-GS/s Two-Stage Pipelined-SAR ADC With 4-bit/Cycle Sub-Quantizer and Reconfigurable Miller-Compensated Three-Stage Amplifier

A 14-bit 1-GS/s Two-Stage Pipelined-SAR ADC With 4-bit/Cycle Sub-Quantizer and Reconfigurable Miller-Compensated Three-Stage Amplifier 150 150
Author(s): Guo Wei, Rui Zhang, Peng Wang, Fule Li, Hanjun Jiang, Zhihua Wang

Abstract:

This article presents a 14-bit 1-GS/s pipelined successive-approximation register (SAR) analog-to-digital converter (ADC) in a 28 nm CMOS process, targeting the optimization of conversion speed and latency. The implemented ADC adopts a two-stage architecture that integrates a residue amplifier (RA) assisted 4-bit/cycle sub-quantizer to tackle the accuracy bottleneck of …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3738437
Publisher: IEEE

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A Low-Power G M-C-Based Continuous-Time ΔΣ ADC With Capacitive Input Feedforward and Duty-Cycled G M Technique

A Low-Power G M-C-Based Continuous-Time ΔΣ ADC With Capacitive Input Feedforward and Duty-Cycled G M Technique 150 150
Author(s): Linran Zhao, Yiming Han, Yaoyao Jia

Abstract:

This article presents a low-power continuous-time (CT) $G_{mathrm {M}}$ -C-based $Delta Sigma $ analog-to-digital converter (ADC) employing capacitive input feedforward and a duty-cycled $G_{mathrm {M}}$ technique to enhance linearity while maintaining high energy efficiency. The ADC employs a CT capacitive network for concurrent signal summation and quantization, enabling input …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 12
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3733305
Publisher: IEEE

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A 100+Gb/s 252–283-GHz RF-Amplifier-Integrated TX/RX Chipset in Standard 65-nm Bulk CMOS

A 100+Gb/s 252–283-GHz RF-Amplifier-Integrated TX/RX Chipset in Standard 65-nm Bulk CMOS 150 150
Author(s): Zhicheng Lin, Hiu Lok Tam, Hao Guo, Xiaoyue Xia, Zijun Guo, Kam Man Shum, Pui-In Mak, Chi Hou Chan

Abstract:

This article presents a 252–283-GHz amplifier-last transmitter (TX) and amplifier-first receiver (RX) wireless front end in standard 65-nm bulk CMOS technology, targeting IEEE 802.15.3d/802.15.3-compliant high-speed point-to-point wireless communications. To overcome the challenges of limited transistor gain and high passive loss that often limit the implementation of J-band RF amplifiers, …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3730962
Publisher: IEEE

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A 1.6-GS/s 13.9-mW 80.2-dB SFDR Single-Channel Pipelined ADC With Dual-Phase Hybrid Amplification

A 1.6-GS/s 13.9-mW 80.2-dB SFDR Single-Channel Pipelined ADC With Dual-Phase Hybrid Amplification 150 150
Author(s): Hongjiang Chen, Jingxiang Wang, Kaize Zhang, Shizhan Mo, Liang Qi, Chao Zhao, Hao Zhang, Zhang Zhang, Sai-Weng Sin, Rui P. Martins, Mingqiang Guo

Abstract:

In this article, we present a 1.6-GS/s single-channel pipelined analog-to-digital converter (ADC). In high-speed ADC designs, residue amplifiers (RAs) face stringent constraints on their amplification time and accuracy. To relax these requirements, first, we propose a dual-phase amplification stage to isolate the serial operations between the second-stage sampling and …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3730470
Publisher: IEEE

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A 10-bit Source-Driver IC for High-Resolution OLED-on-Silicon Displays With All-Channel Automatic Offset Calibration and Data-Aware Slew-Rate Enhancement

A 10-bit Source-Driver IC for High-Resolution OLED-on-Silicon Displays With All-Channel Automatic Offset Calibration and Data-Aware Slew-Rate Enhancement 150 150
Author(s): Junghwan Oh, Wiman Yoo, Dong-Kun Lee, Dong-Hyun Kim, Jong-Seok Kim

Abstract:

This article presents a 10-bit source-driver (SD) IC for high-resolution OLED-on-silicon (OLEDoS) microdisplays in augmented reality (AR)/virtual reality (VR) applications. To address the stringent constraints of aggressive area scaling, sub-microsecond settling time, and high output uniformity, three key techniques are proposed. First, a demultiplexer (DEMUX)-based channel width expansion …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3726042
Publisher: IEEE

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A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications

A 1.2-V, 8.5-ns Settling, Bi-Slewing CMOS Driver for Heavy Loads in Discrete-Time Analog Computing Applications 150 150
Author(s): Maysara Hamada, Mostafa Toubar, Zixu Wang, Nishant Bakshi, Hsiang-Chun Cheng, Mayank Palaria, Joshua Yang, Mike Shuo-Wei Chen

Abstract:

As crossbar-based analog computing grows in popularity for high-speed, energy-efficient processing, the need to drive discrete-time signals to heavy loads arises. This letter presents a novel bi-slewing CMOS driver utilizing high slew-rate error amplifiers and a push–pull stage. The proposed driver achieves a measured settling time of 8.5 ns and …

Published in: IEEE Solid-State Circuits Letters
Page(s): 218 – 221
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3717852
Publisher: IEEE

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A 0.0035-mm2 86-dB-SNR 1.25-MHz-BW Noise-Shaping SAR ADC Enabling kT/C Noise Shaping

A 0.0035-mm2 86-dB-SNR 1.25-MHz-BW Noise-Shaping SAR ADC Enabling kT/C Noise Shaping 150 150
Author(s): Xing Wang, Zhishuai Zhang, Yi Zhong, Nan Sun, Lu Jie

Abstract:

This work presents a compact second-order noise shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) featuring a novel kT/C noise shaping technique. The proposed kT/C noise shaping technique selectively suppresses kT/C noise within the signal bandwidth of an oversampled SAR ADC. It avoids using a wideband noise …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 2798 – 2808
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3616265
Publisher: IEEE

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A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension

A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension 150 150
Author(s): Michele Rocco, Gabriele Zanoletti, Alessia Ceroni, Giacomo Tombolan, Gabriele Bè, Luca Ricci, Salvatore Levantino, Andrea L. Lacaita, Luca Bertulessi, Carlo Samori, Andrea G. Bonfanti

Abstract:

The pipeline-successive approximation register (SAR) analog-to-digital converter (ADC) extends the energy efficiency and the scaling properties of SAR ADCs to the medium-to-high resolutions and high bandwidths typical of classical pipeline ADCs. However, the residue amplifier (RA) is often a performance and energy efficiency bottleneck, especially for high-speed designs in scaled …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715775
Publisher: IEEE

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