3-D packaging

  • No Comments

A 56-Gb/s Hybrid Silicon Photonic and 5-nm CMOS 3-D-Integrated Transceiver for Optical Compute I/O

A 56-Gb/s Hybrid Silicon Photonic and 5-nm CMOS 3-D-Integrated Transceiver for Optical Compute I/O 150 150
Author(s): Ganesh Balamurugan, Parmanand Mishra, Subal Sahni, Ankur Aggarwal, Simon Forey, Andrew Gimlett, Prateek Goyal, Han Hao, Santosh Hariwan, Masum Hossain, Sejun Jeon, Narayan Kaniyur, David Lazovsky, Wonho Lee, Bengt Littmann, Raj Nagulapalli, Kevin Park, John Rollinson, Matteo Staffaroni, Prakash Thakur, Saurabh Vats, Preet Virk, Dehua Xiao, Hemesh Yasotharan, Raman Yazdani, Waleed Younis, Shifeng Yu, Phil Winterbottom

Abstract:

This work presents a hybrid 3-D-integrated silicon photonic (SiPh) transceiver suitable for realizing chiplet-based optical I/O in future AI/ML ASIC packages. The optical transceiver die stack is composed of two ICs: a SiPh IC (PIC) with micrometer-scale, thermally robust electro-absorption modulators (EAMs), and a 5-nm CMOS electronic IC (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3655295
Publisher: IEEE

View on IEEE Xplore

Search this website