Open to Both Undergraduate and Graduate Students
- The goal of this challenge is to design an integrated circuit by using the greatest number of components picked from the provided list (no other components should be used except the ones in the provided list, and no other components should be needed to make the circuit work [this includes additional inputs for bias voltages, digital functionality that is not implemented by your used devices, etc])
- The circuit does not have to be original and/or optimized, although proper functionality is expected (e.g., an amplifier has to amplify, an oscillator has to oscillate, etc.)
- Besides the number of components used out of the list provided, the evaluation committee will judge creativity, the rationale and practicality of the solution proposed, and the circuit characterization (i.e., analysis and simulation results provided)
- The circuit can be implemented in any IC-technology available to you that has both NMOS and PMOS-transistors. (Please state the technology adopted in your submission and how this affected your design.)
Some Rules Must be Followed
- The circuit must have one voltage supply (VDD) compatible with the technology you use
- Each component in the list can be used only once
- The use of each component must be necessary for the proper functionality of the circuit (e.g., no dummy components)
- The circuit must have at least one identified output
- The circuit may either be (1) autonomous, (2) have an arbitrary input that needs to be measured, e.g., a variable resistance in a Wien-bridge, or (3) needs a specific input, e.g,. an input signal for an amplifier, or an LO for a frequency divider. For (2) and (3), an ideal input voltage source or component may be included in the circuit and/or testbench, but only connected between the designated input terminals.
- The circuit must be simulated, and simulation results must be provided to demonstrate the desired functionality
List of Components
- Ideal constant voltage supply (VDD)
- Ideal ground (GND)
- Ideal DC current source or ideal DC voltage source
- 10 identical NMOS-devices, 0.2 <= W/L <= 20, some of which must be put in parallel to form at most 4 separately identifiable transistors
- 10 identical PMOS-devices, 0.2 <= W/L <= 20, some of which must be put in parallel to form at most 4 separately identifiable transistors
- 1 NMOS-device, W/L = 0.1
- 1 PMOS-device, W/L = 0.1
- 2 identical NMOS-devices, W/L = 40
- 2 identical PMOS-devices, W/L = 40
- 3 passive components from the following list (any combination is allowed, including multiple identical components)
- Ideal capacitor C, with 1fF <= C <= 100pF
- Ideal resistor R, with 10Ω <= R <= 1MΩ
- Ideal inductor L, with 100pH <= L <= 10nH
- Ideal transformer, with Lp, Ls >= 100pH, Lp+Ls <= 5nH, coupling factor 0 < k <= 1
- Ideal diode D, obeying the Shockley equation
- Ideal transmission line TL, with 20Ω <= Z0 <= 200Ω, and length <= 1mm
Submission Instructions and Deadlines
- You must be an undergraduate or graduate student enrolled in a college or university at the submission deadline of the contest to enter the contest. You do not have to be an SSCS member to submit to the contest; however, you must be an IEEE member. Your IEEE membership number will be required to enter the contest.
- Submissions must be either individual or in teams of two. The conference awards are “lump sum”, i.e., teams will have to share the prize.
- Each individual is allowed only one submission, whether individual or as part of a team. When there are multiple ideas, the student is encouraged to select the best one for submission.
- Please read the Contest Rules and Regulations here
- Please download the template (PDF Format) to explain your answer.
- Your answer must be no more than two-pages in the IEEE paper style. Acknowledgments, references, and author bio do not count towards the page limit.
- Upload your answer here and fill out the submission form – Deadline is May 31, 2026 (use any timezone to your advantage).
Awards
- Up to three submissions with the best answers will receiver US$2K each towards attending an SSCS-sponsored conference of their choice (ISSCC, CICC, ESSERC, VLSI Symposium, ASSC). Regardless of which of the five conferences is chosen, it must be the edition immediately following the winners’ notification. This award will be paid as a reimbursement following the attended conference.
- All submitters with a sound submission will receive one year of free membership in the Solid-State Circuits Society.
Mark Oude Alink
Chair of the SSCS Student Circuit ContestWinners
| Contest Year | Winner Name | School Name | Contribution |
|---|---|---|---|
| 2025 | Zhishuai Zhang | ETH Zürich, Switzerland, & Tsinghua University, China | See the 2025 Winners’ contributions |
| Ercem Yesil | University of California, Los Angeles, USA | ||
| 2024 | Jakob Finkbeiner | University of Stuttgart, Stuttgart, Germany | See the 2024 Winners’ contributions |
| 2023 | Jahan Razavi | University of Michigan, USA | See the 2023 Winners’ contributions |
| Sumukh Nitundil | Indian Institute of Technology Bombay, India | ||
| Ahmed Elmenshawi | Rensselaer Polytechnic Institute, USA | ||
| 2022 | Michelle Chow | University of Calgary, Canada | See the 2022 Winners’ contributions |
| Kshitiz Tyagi | Indian Institute of Technology Gandhinagar, India | ||
| Matias Jara | Universidad de Concepción, Chile | ||
| 2021 | Anoop Narayan Bhat | University of Twente, The Netherlands | See the 2021 Winners’ contributions |
Questions?
If you have any questions regarding the contest, please contact us.