residue amplifier (RA)

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A 77-dB DR Two-Stage SAR ADC for Low-Gain Analog Front-Ends Using Asynchronous Pipelining and RC Snubber Reference Stabilization

A 77-dB DR Two-Stage SAR ADC for Low-Gain Analog Front-Ends Using Asynchronous Pipelining and RC Snubber Reference Stabilization 150 150
Author(s): Jun Feng, Rares Bodnar, Roberto Maurino, Marcel J. M. Pelgrom, Filip Tavernier

Abstract:

The analog front-end (AFE) often bottlenecks the power of modern receiver chains, burdened by the large-signal linearity required before the ADC. This work introduces a 77-dB DR, 200-MS/s two-stage SAR ADC that can alleviate much of this burden by offering a significantly lower input-referred noise (IRN) to enable low-gain …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 11
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3686660
Publisher: IEEE

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An 800-MS/s 13-b 2× TI Pipelined-SAR ADC With Rapid Digital Amplification

An 800-MS/s 13-b 2× TI Pipelined-SAR ADC With Rapid Digital Amplification 150 150
Author(s): Peizhe Li, Danfeng Zhai, Qi Liu, Chixiao Chen

Abstract:

This work proposes a rapid digital amplification (RDA) with residue-aware reference, offering an equivalent open-loop (OL) gain enhancement of 25 dB and reducing the interstage gain error (ISGE)-induced SNR degradation by 20 dB, with an extra amplification latency of only 200 ps. It is implemented in an 800-MS/s 13-b two-way time-interleaved (…

Published in: IEEE Solid-State Circuits Letters
Page(s): 137 – 140
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3684735
Publisher: IEEE

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