low noise

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Minimizing the Noise in Low-Current Sensing by MOSFET PN-Junction Diode Feedback

Minimizing the Noise in Low-Current Sensing by MOSFET PN-Junction Diode Feedback 150 150
Author(s): Ehsan Semsar Parapari, Marco Bennati, Michele Biondi, Marco Crescentini, Federico Thei

Abstract:

This letter proposes a transimpedance amplifier (TIA) architecture that minimizes noise for continuous-time (CT) low-current sensing. The approach leverages a MOSFET to realize a pure PN-junction diode as the TIA feedback element, such that MOS channel conduction is completely suppressed. Therefore, channel-induced noise contributions associated with conventional MOS-based feedback TIAs …

Published in: IEEE Solid-State Circuits Letters
Page(s): 1 – 1
Year of Publication: 2026
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2026.3692971
Publisher: IEEE

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A 60-GHz Low-Noise mmWave Divider-Less Fractional-N Cascaded PLL Achieving −250.2-dB FoMJ in 28-nm CMOS

A 60-GHz Low-Noise mmWave Divider-Less Fractional-N Cascaded PLL Achieving −250.2-dB FoMJ in 28-nm CMOS 150 150
Author(s): Jaehong Jung, Eunseok Lee, Donghyeon Han, Jinchen Wang, Anantha P. Chandrakasan, Ruonan Han

Abstract:

This article presents a fractional- ${ {N}}$ cascaded phase-locked loop (PLL) operating in the mmWave band from 55.8 to 64.2 GHz. The cascaded architecture consists of a first-stage fractional- ${ {N}}$ reference-sampling (RS) PLL and a second-stage sub-sampling (SS) PLL, incorporating two key innovations. The first-stage RS-PLL leverages a fully differential voltage-domain quantization-noise cancellation (…

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3652928
Publisher: IEEE

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Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS

Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS 150 150
Author(s): Anojh Kumaran Rajendra, Harijot Singh Bindra, Bram Nauta

Abstract:

This article introduces two comparators featuring a dynamic-bias preamplifier and self-clocked latches, tailored for ultra-low-power and medium-speed applications with <500- $\mu $ V input-referred noise (IRN). The proposed self-clocked latches are activated by the preamplifier outputs and therefore operate with a lower common-mode current, which in turn minimizes the crowbar current …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3612157
Publisher: IEEE

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A 0.5-/0.95-dB NF, 50-/25-Ω Configurable CMOS Front-End ASIC for the Readout of Liquid Argon Calorimeter in the LHC

A 0.5-/0.95-dB NF, 50-/25-Ω Configurable CMOS Front-End ASIC for the Readout of Liquid Argon Calorimeter in the LHC 150 150
Author(s): Mietek Dabrowski, Filip Tavernier, Paul Leroux

Abstract:

This article presents the design of a four-channel front-end application specific integrated circuit (ASIC), ATLAS liquid argon front-end (ALFE), developed for the readout of the liquid-argon calorimeter (LAr) detector in the ATLAS experiment at the Large Hadron Collider (LHC). ALFE enables the readout of current signals induced in the LAr …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 15
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3602751
Publisher: IEEE

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