Integrated circuit modeling

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Non-Volatile ReRAM-Based Compact Event-Triggered Counters

Non-Volatile ReRAM-Based Compact Event-Triggered Counters 150 150
Author(s): Moin Diwan, Shengchao Zhang, Zidu Li, Alex James, Bhaskar Choubey

Abstract:

With an increasing number of transistors per circuit, the fabrication cost and the energy consumption of each integrated circuits increase exponentially, which drives the need to reduce the number of transistors. In this study, we explore a novel design for a 16-bit digital counter that utilizes a combination of complementary …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 131 – 138
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3619415
Publisher: IEEE

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Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model

Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model 150 150
Author(s): Mohammad Adnaan, Saeideh Alinezhad Chamazcoti, Emil Karimov, Marie Garcia Bardon, Francky Catthoor, Jan van Houdt, Azad Naeemi

Abstract:

We present a framework for design technology co-optimization (DTCO) of the main memory system with one transistor-one capacitor (1T1C) ferroelectric random access memory (FERAM) as an alternative to dynamic random access memory (DRAM). We start with the ferroelectric capacitor device model and perform array-level memory circuit simulation. Then, we …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 99 – 106
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3618883
Publisher: IEEE

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A 4 × 50 Gb/s 2.9-pJ/b NRZ VCSEL-Based Co-Packaged Optical Link With Fiber Termination

A 4 × 50 Gb/s 2.9-pJ/b NRZ VCSEL-Based Co-Packaged Optical Link With Fiber Termination 150 150
Author(s): Sashank Krishnamurthy, Susnata Mondal, Junyi Qiu, Joseph Kennedy, Soumya Bose, Tolga Acikalin, Shuhei Yamada, James Jaussi, Mozhgan Mansuri

Abstract:

A four-channel vertical cavity surface-emitting laser (VCSEL)-based co-packaged optical (CPO) transceiver (TRX) is demonstrated, integrating a photodiode (PD) array, a trans-impedance amplifier front-end integrated circuit (TIA-FE IC), an electrical receiver (RX) IC, and optical fiber termination on a single package on the receive side. The transmitter (TX) counterpart incorporates …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 16
Year of Publication: 2025
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2025.3600662
Publisher: IEEE

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Polar-Axis Orientation Fluctuations and the Impact on the Intrinsic Variability in Ferroelectric Capacitors

Polar-Axis Orientation Fluctuations and the Impact on the Intrinsic Variability in Ferroelectric Capacitors 150 150
Author(s): Wei Zhang, Jianze Wang, Xuanyao Fong

Abstract:

We utilized phase-field simulations to investigate the effects of polar-axis (PA) orientation fluctuations on the extrinsic properties of single ferroelectric (FE) grains, focusing on the coercive electrical field (EC) and the remnant polarization (Pr). The underlying mechanisms through which PA orientation fluctuations influence polarization behavior are studied to gain insights …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 74 – 80
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3586589
Publisher: IEEE

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A 302.5-GHz 30.9-dB-Gain THz Amplifier in 65-nm CMOS

A 302.5-GHz 30.9-dB-Gain THz Amplifier in 65-nm CMOS 150 150
Author(s): Yu-Kai Chen, Yi-Fan Tseng, Wei-Zhe Su, Chun-Hsing Li

Abstract:

A 302.5-GHz high-gain CMOS THz amplifier is proposed in this work. An electromagnetic (EM) modeling approach, verified by transistor measurements, is employed to optimize transistor layout, effectively reducing gate resistance and drain-to-gate capacitance. This significantly enhances the transistor’s maximum oscillation frequency $f_{mathrm {max }}$ from 239.7 to 367.5 GHz. Furthermore, a $…

Published in: IEEE Solid-State Circuits Letters
Page(s): 165 – 168
Year of Publication: 2025
Electronic ISSN: 2573-9603
DOI: 10.1109/LSSC.2025.3574413
Publisher: IEEE

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CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability

CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability 150 150
Author(s): Sufia Shahin, Swati Deshwal, Anirban Kar, Mahdi Benkhelifa, Yogesh S. Chauhan, Hussam Amrouch

Abstract:

This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging effects. A rigorously calibrated TCAD model, validated against experimental CFET data, is employed to quantify the impact of metal gate granularity (MGG)-induced …

Published in: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Page(s): 51 – 59
Year of Publication: 2025
Electronic ISSN: 2329-9231
DOI: 10.1109/JXCDC.2025.3568622
Publisher: IEEE

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