Antennas

A 3.47 NEF 175.2-dB FoMs Direct Digitization Front-End Featuring Delta Amplification Noise-Shaping SAR ADC for Biosignal Acquisition

A 3.47 NEF 175.2-dB FoMs Direct Digitization Front-End Featuring Delta Amplification Noise-Shaping SAR ADC for Biosignal Acquisition 150 150

Abstract:

This article presents a direct-digitization interface for ExG bio-signals’ readout that simultaneously achieves a high dynamic range (DR) and a low noise-efficiency factor (NEF). The proposed delta amplification (DA) and feedback cancellation technique reduce both the input and output ranges of the first amplifier, thus allowing the use of a …

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A 10.1-ENOB 8kHz Bandwidth 95–250nW PVT-Robust DT Level-Crossing ADC for Sparse and Generic Signals

A 10.1-ENOB 8kHz Bandwidth 95–250nW PVT-Robust DT Level-Crossing ADC for Sparse and Generic Signals 150 150

Abstract:

This article presents an event-driven discrete-time level crossing analog-to-digital converter (DT-LCADC) that is energy-efficient in converting both sparse and generic signals and is robust against process voltage and temperature (PVT) variations. The proposed DT-LCADC uses the comparator delay to classify each level-crossing event as slow (produced by a small input …

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A 28-nm System-in-One-Macro Computing-in-Memory Chip Utilizing Leakage-Eliminated 2T1C and Capacitor-Over-Logic 1T1C eDRAM

A 28-nm System-in-One-Macro Computing-in-Memory Chip Utilizing Leakage-Eliminated 2T1C and Capacitor-Over-Logic 1T1C eDRAM 150 150

Abstract:

Computing-in-memory (CIM) is a promising paradigm for energy- and area-efficient implementation of the heavy general matrix multiplication (GEMM) operations, especially in the evolving deep learning algorithms. Though existing CIM macros have demonstrated remarkable energy/area efficiency, the corresponding metrics of the system-level CIM chips degrade due to the peripheral components, …

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A 16× Interleaved 32-GS/s 8b Hybrid ADC With Self-Tracking Inter-Stage Gain Achieving 44.3-dB SFDR at 20.9-GHz Input

A 16× Interleaved 32-GS/s 8b Hybrid ADC With Self-Tracking Inter-Stage Gain Achieving 44.3-dB SFDR at 20.9-GHz Input 150 150

Abstract:

This article presents a 32-GS/s 16-channel hierarchical time-interleaved (TI) hybrid analog-to-digital converter (ADC). The prototype utilizes the intrinsic high-speed quantization of time-domain (TD) ADC to reduce the interleaving factor. By incorporating hierarchical sampling and a cascode sampler, the compact TI-ADC achieves 44.3-dB spurious-free dynamic range (SFDR) at 20.9-GHz input. …

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A 0.4-V 988-nW Tiny Footprint Time-Domain Audio Feature Extraction ASIC for Keyword Spotting Using Injection-Locked Oscillators

A 0.4-V 988-nW Tiny Footprint Time-Domain Audio Feature Extraction ASIC for Keyword Spotting Using Injection-Locked Oscillators 150 150

Abstract:

This work presents an injection-locked oscillator (ILO)-based feature extraction (FEx) system. It combines voltage- and time-domain signal processing to implement a power-efficient programmable gain amplifier (PGA) and a small-footprint, high-selectivity ILO-based voltage-to-time converter bandpass filter (VTC-BPF) bank and rectifier. The VTC-BPF enables direct analog-to-time conversion, eliminating the need for …

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A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction

A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM With Metal Wire-R Tracking and Sequential Access-Aware Dynamic Power Reduction 150 150

Abstract:

This article presents a 2-read/write (2RW) pseudo dual-port (PDP) static random access memory (SRAM) macro implemented in advanced 3nm Fin-FET technology, achieving a competitive bit density of 19.87Mbit/mm2 for advanced nodes. To address challenges in process scaling, reliability under process voltage temperature variations, and dynamic power consumption, two …

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A Continuous-Time Zoom Sensor Readout Frontend With Fast Tracking and Floating-Gm-CCO Integrator

A Continuous-Time Zoom Sensor Readout Frontend With Fast Tracking and Floating-Gm-CCO Integrator 150 150

Abstract:

Emerging edge applications processing weak signals in noisy environments demand sensor readout frontends with low noise, low power, high dynamic range (DR), and high input impedance. This article presents a zoom sensor readout frontend design that can track signals with rapid changes over a wide DR with high energy efficiency. …

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A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference

A 28-nm Digital Transpose SRAM Compute-in-Memory Macro With Accurate/Approximate Dual Mode for Floating-Point Edge Training and Inference 150 150

Abstract:

Static random-access memory (SRAM)-based computing-in-memory (CIM) macros have been widely studied to improve the energy efficiency of edge artificial intelligence (AI) inference tasks. However, less attention has been given to AI training, which requires CIM macros to not only perform matrix multiply-accumulate (MAC) operations but also support matrix transposition. …

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A Reconfigurable Multimode Readout IC for Nonconductive and Capacitive Sensing With 33.9-dB SNR on 6.5-in AMOLED Panels

A Reconfigurable Multimode Readout IC for Nonconductive and Capacitive Sensing With 33.9-dB SNR on 6.5-in AMOLED Panels 150 150

Abstract:

This letter presents a multimode readout IC for 6.5-in 34Tx/16Rx on-cell touch AMOLED (OCTA) panels, detecting both conductive and nonconductive objects (NCos) without panel modifications. To enable this dual detection, a reconfigurable analog front-end (AFE) is proposed, functioning as either a capacitance-to-voltage converter or a triboelectric charge sampler. In …

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