Special Issue on High-Performance Frequency Synthesizers
OJ-SSCS Special Issue on High-Performance Frequency Synthesizers
Frequency synthesizers are among the most critical blocks in wireless, wireline, and digital clocking applications. Several advances have been done in recent years bringing the rms integrated jitter of multi-GHz frequency sources below the barrier of 100 fs, and demonstrating direct modulation of phase-locked loops at wide bandwidth. Next generation 5G/6G communication and sensing applications require local oscillators (LOs) with even higher spectral purity, at lower power consumption and higher frequency. Besides that, clock generators at increasingly lower jitter are demanded in wireline and digital applications, as well as in clocking of ultra-high-resolution analog-to-digital converters.
This special issue aims to cover the latest advances in frequency synthesis circuits and systems to efficiently generate LO signals with low phase noise, low spurious tones, and large modulation bandwidth. The issue aims to target designs for high-performance local oscillators in wireless communications, millimeter-wave frequency synthesis, radar systems, low-power sensor networks, wireline applications, and clock generation for data converters and digital systems. Original research contributions describing new integrated circuits and systems are desired, along with in-depth and comprehensive review articles.
Authors are invited to submit papers following the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) guidelines, within the remit of this Special Section call. Topics include (but are not limited to):
- Frequency synthesizers for wireless communications
- Millimeter-wave frequency synthesizer architectures
- Frequency synthesizers for radar systems
- Low-power frequency synthesis for sensor networks
- Direct phase/frequency modulators
- Phase-locked loops for wireline applications
- Clock generation for digital systems
Submission Guidelines: All submitted manuscripts must
(i) conform to OJ-SSCS' normal formatting requirements and page count limits;
(ii) incorporate no less than 70% of new (previously unpublished) material;
(iii) validate principal claims with experimental results;
(iv) be submitted online at: https://mc.manuscriptcentral.com/oj-sscs
Please note that you need to select “High-Performance Frequency Synthesizers” when you submit a paper to this Special Issue.
Deadlines
Special Section Open for Submissions: March 1, 2024
Paper Submission Deadline: May 24, 2024
First Notification: July 15, 2024
Revision Submission: August 15, 2024
Final Decision: September 15, 2024
Publication Online: October 15, 2024
Guest Editors
Prof. Salvatore Levantino, Politecnico di Milano, salvatore.levantino@polimi.it
Dr. Wanghua Wu, Samsung Semiconductor, wanghuawu@gmail.com