Wide power-performance adaptation is becoming crucial in always-on nearly real-time and energy-autonomous integrated systems that are subject to wide variability in the power availability and the performance target. Adaptation is indeed a prerequisite to assure continuous operation in spite of the widely fluctuating energy/power source (e.g., energy harvester), and to grant swift response upon the occurrence of events of interest (e.g., on-chip data analytics), while maintaining extremely low consumption in the common case. These requirements have led to the strong demand of a new breed of integrated systems having an extremely wide performance-power scalability and adaptation, beyond conventional voltage scaling or adaptive parallelism. In this talk, new techniques that drastically extend the performance-power scalability of digital circuits and architectures are presented. Silicon demonstrations of better-than-voltage-scaling adaptation to the workload are illustrated for both the data path (i.e., microarchitecture) and the clock path. Adaptation to a very wide range of energy/power availability is also discussed, presenting demonstrations of always-on systems (e.g., microcontrollers, power management units) with power down to sub-nW, and duty-cycled operation down to pW range. Several silicon demonstrations are illustrated to quantify the benefits offered by wide power-performance adaptation, and identify opportunities and challenges for the decade ahead.

The historical 100X/decade energy down-scaling is currently being threatened by the end of Moore’s law, and the limited prospective energy gains from approaches that have been already exploited extensively (e.g., heterogeneous systems, ultra-low voltage, parallelism). Major shifts from traditional sensing/processing paradigms are now mandatory, and new design dimensions that enable further energy reductions need to be explored, to sustain continuous miniaturization, lifetime and cost improvements.
In this talk, energy-quality (EQ) scalable circuits and systems are introduced as a fundamental direction to continue the historical exponential energy down-scaling. The CAS community is currently focusing on this new field, which is also the theme of major journal special issues. EQ-scalable systems dynamically and explicitly trade off energy and quality from sensor to circuit, architecture, algorithm, and up to system level. Recent and novel approaches are discussed to minimize the energy at run time, based on the actual quality target that is set by the specific task, the context, and the specific dataset at hand. Quality is treated as an explicit knob, eliminating the quality slack that is traditionally imposed by worst-case design across different applications, contexts, datasets, and the pessimistic design margin to counteract process/voltage/temperature variations. Interesting convergence with machine learning and other important applications is discussed to provide an insight into the inter-dependence of algorithms, architectures and circuits. Several silicon demonstrations are illustrated to quantify the benefits offered by energy-quality scaling, and to describe the challenges that need to be solved to fulfill its potential.

Batteries pose fundamental threats to the further advancement of systems for ubiquitous sensing and intelligence (e.g., Internet of Things, devices for healthcare, smart objects/systems). Batteries are indeed a major cost and form factor bottleneck in single-chip integrated systems, and will also have a very heavy environmental impact when deployed (and disposed) at the expected scale of one trillion connected devices.
In this talk, state-of-the-art techniques for battery-lightweight and battery-less integrated systems with always-on operation are introduced. From a top-down viewpoint, system architectures are introduced to enable continuous adaptation to workload and harvested power/battery energy availability. Time- and event-driven frameworks are introduced and exemplified with several silicon demonstrations, along with duty-cycled and always-on schemes. From a bottom-up perspective, advanced circuit techniques are introduced to enable uninterrupted operation under uncommonly wide range of available harvested power, and/or very limited battery energy. The talk covers all major sub-systems along the on-chip signal chain, from energy harvesting to power delivery, analog interfaces, digital processing, and higher-level signal sensemaking. Edge computing, machine intelligence and in-memory computing are discussed as crucial enablers of continuous event monitoring and efficient energy usage at the system level. The related concepts are exemplified by integrated prototypes from industry and academia.

Security is finally being generally perceived (and often required) as an important attribute of hardware systems, as a result of several breaches and vulnerabilities that have been brought to the attention of the general public. Hardware security is now progressively becoming closer to ubiquitous in space and always-on in time, as the related building blocks and sub-systems need to be an essential part of any integrated system down to tightly power-constrained systems (e.g., nodes for the Internet of Things).
In this talk, pervasive hardware security is discussed in a broad sense, encompassing methods that assure security in every System on Chip (SoC), as well as in critical SoC components. From an SoC viewpoint, recent trends in energy efficiency are analyzed and put in perspective to identify the opportunities to embed security solutions down to low-end SoCs and in an always-on fashion. From an SoC component viewpoint, immersed-in-logic security primitives are discussed to highlight how security can be pervasive within each component, while keeping the system integration effort to a minimum. Cost-aware design methods are also discussed, being cost a major factor that decides whether a security feature is incorporated in real-world systems or not. Several silicon demonstrations are illustrated to quantify the benefits and the limits of existing techniques, and identify opportunities and challenges for the decade ahead. At the end of the talk, fundamental directions on how to make hardware security more pervasive and unceasing are discussed.

Over the last few years, a significant growth of the research involving the use of microwaves to image the human body has been taking place. Among the many examples of ongoing research, the use of microwaves for breast cancer diagnostic imaging has seen an increasing interest. Ultra wideband microwave radar imaging can effectively complement conventional diagnostic techniques, e.g. X‐ray, MRI, ultrasound, yielding higher sensibility and specificity, lower cost, and smaller size, hence emerging as an enabling technology for mass screening programs. Ultra wideband radars can be realized in different technologies, discrete or fully integrated. This talk investigates the typical system and circuit-level challenges of such radars, and discusses some implementation examples. The talk presents innovative circuit solutions addressing the challenges set by the ultra wideband frequency range of operation of the radar transceiver. Due to their broadband operation, such design techniques may find application in other wideband systems.

Integrated magnetic transformers are becoming ubiquitous in mm-wave and RF systems, while also finding application in fully-integrated dcdc converters. This talk will cover the fundamentals of the transformer operation spanning from the underlying physical principles, to the link between the magnetic parameters (inductances and magnetic coupling) and the geometry of the device, to its use in the design of building blocks like LNA’s, PA’s, VCO’s, etc. The advantages and possibilities of using a transformer for the implementation of baluns, impedance transformation networks, higher-order resonant networks, feedback circuits, etc., will be highlighted.

The talk will deal with the design of low-phase noise voltage-controlled harmonic oscillators (VCOs) implemented in bipolar technologies. The design challenges related to achieving minimum phase noise for a given set of technology parameters (supply voltage, metal stack, varactor devices, etc.) will be discussed with particular emphasis to attaining low phase noise while using varactor diodes, to the use of magnetic transformers in the resonator, and to the selection of the most appropriate oscillator topology. Effective techniques to tackle such issues will be illustrated. Design examples of VCOs operating in the K-band and suitable for 5G applications will be presented.

Cellular technology has witnessed five generations of evolution - the mobile UE-era ushered in by 2G (GSM/EDGE), to the future smart-phones that will powered by the enhanced spectral efficiency of 5G. Each 'G' improved the user experience while introducing new hardware design challenges. I compare 2/3/4/5G system requirements, derive key TX/RX/LO circuit specifications, and highlight the differences in circuit topologies suited for these contrasting specifications. Using this framework, circuit techniques to handle a diverse range of problems such as low phase-noise oscillators, improved blocker tolerance, single-RB linearity will be introduced.

The explosive growth services delivered via the internet onto the mobile handset has result in an insatiable demand for higher data-rates. Millimeter-wave CMOS radios – a research topic for over a decade – is now finally on the cusp of large-scale deployment. In this talk I will describe the challenges and state-of-the-art in circuits and architectures for 28GHz/38GHz 5G NR transceivers targeting user-equipment or UE applications.

Modern SoCs for advanced applications are integrating an increasing number of phase-locked loops (PLLs) into a single silicon die. 5G transceivers require multiple PLLs to implement complex schemes of carrier aggregation and MIMO. Multi-core processors also have to use many PLLs to generate independent clock frequencies for each core to operate at the optimum performance. With this trend, an area-efficient design of PLLs becomes more important. In this point of view, i.e., the efficiency in the use of silicon, ring-oscillator-based digital PLLs (DPLLs) have obvious merits over conventional LC VCO-based charge-pump PLLs. Ring-oscillator-based DPLLs also have an advantage in terms of the scalability with new CMOS technologies. They also can be implemented in some CMOS technologies where high-quality metal layers for inductors are not available. Despite foregoing merits, their poor jitter performance has limited their popularity in high-performance applications that generally require a clock signal having an ultra-low jitter. This lecture introduces recent architectures of low-jitter ring-oscillator-based DPLLs and presents key enabling circuit techniques to resolve their problems, such as thermal and flicker noises of ring oscillators, reference spurs, and fractional spurs. Finally, we discuss the limit of ring-oscillator-based DPLLs and the possibility of their adaptation to high-performance applications.

As the data rates of both wireless and wireline communication systems increase, the generation of millimeter-wave-band (mmW-band) signals that have ultra-low phase noise becomes more important for the design of the transceivers. The standard of the fifth-generation (5G) mobile system defines new radio frequencies in mmW bands from 24 to 40 GHz. To support high-order modulations, such as 256 QAM, the value of the EVM must be reduced to less than –30 dB, implying that mmW-band local-oscillating signals must have an extremely low IPN, e.g., less than −36 dBc. Similarly, to satisfy the Nyquist criterion and minimize the effect of channel mixing, direct RF-data converters using high-speed analog-to-digital converters (ADCs) also require mmW-band clock signals that have very low RMS jitter. The demands on the performance of the ultra-low jitter for mmW-band signals also have increased recently in advanced, high-speed serial links, in which the target data rates have increased to more than 100 Gb/s. As shown above, mmW-band signals are used in many different advanced applications, but they commonly are expected to have sub-100 fs RMS jitter values. This lecture introduces recent architectures of frequency synthesizers that can generate ultra-low-jitter mmW-band signals, based on a cascaded architecture consisting of a ultra-low-jitter GHz-range PLL and a wideband mmW-band injection-locked frequency multiplier.

Continuous increases in the data rates of communication systems demand further improvement in the jitter performance of clock signals. To date, conventional phase-locked loops (PLLs) using an LC-type voltage-controlled oscillator (LC-VCO) have been used the most widely in practical applications. However, the critical problem of LC-VCO-based PLLs is a large silicon area. Ring VCO-based injection-locked clock multipliers (ILCMs) are considered as an alternative solution. In ILCMs, the phase of the output edges of a free-running VCO is corrected naturally by periodically injected reference signals. This phase-realignment mechanism of an ILCM is capable of creating a much higher cutoff frequency of the noise transfer function (NTF) of the VCO compared to conventional PLLs, thereby resulting in the much greater suppression of the jitter of ring VCOs. Despite the superiority of ILCMs in the reduction of the jitter of ring VCOs, ILCMs have a critical problem in that the performances of RMS jitter and reference spur are degraded significantly due to PVT variations. This problem asks for intensive background calibration techniques that can remove any phase errors of ILCMs in a real-time fashion. This lecture presents ring-VCO-based ILCMs that can achieve a low reference spur as well as a low RMS jitter and the design of versatile background calibration techniques that can help ILCMs maintain good jitter performance.

Piezoelectric energy harvester (PEH) is one of the most promising candidate for ambient vibration energy scavenging for ubiquitous miniaturized Internet of Things (IoT) devices. Due to the PEH inherent capacitance, the extractable AC-DC electrical power in traditional PEH interface using full-bridge rectifier (FBR) is limited. Existing PEH interfaces generally employ non-linear techniques such as the parallel-synchronized-switch harvesting-on-inductor (P-SSHI) and fractional open circuit technique to enhance the extracted power and achieve efficient maximum power point tracking (MPPT). However, they typically require bulky external high-Q inductors to extend the damping duration while inducing excessive device voltage stress during MPPT. This talk will focus on the discussion of capacitive PEH interfaces for flipping the PEH voltage for energy extraction improvement. It will first cover the basic operations of capacitive PEH interfaces and provide the fundamental analysis on its performance limits. The design tradeoffs between the achievable extracted energy and the different loss mechanisms will be outlined. System level implementation of maximum power point tracking (MPPT) will also be discussed.

The recent wireless sensing and emerging Internet-of-Thing (IoT) market have enabled the development of miniaturized systems with different application requirements. While highly efficient power management is mandatory to ensure the system performance and operation lifetime, on-chip inductive power converters generally exhibits increased manufacturing cost despite of their higher achievable power densities. Due to the full integration together with high energy efficiency and adaptability, reconfigurable switched-capacitor (SC) DC-DC converters are promising for ultra-compact on-chip power solutions. This talk will first cover the basic operations and control methodologies of SC DC-DC converters. It will then introduce the conventional SC DC-DC topologies, followed by the fundamental analyses and different loss mechanisms. Advanced reconfigurable SC DC-DC converters capable of systematic multiple rational voltage conversion ratio (VCR) generation and their fundamental limits will also be proposed, and further compared with the state-of-the-art. Adaptive gate driving techniques with consistent switch driving voltage while preventing reversion loss under wide voltage dynamics will also be introduced. These techniques enable highly efficient SC power converters with better SoC integration for next generation ultra-compact low-cost IoT devices.

Ultra-low power/energy efficient wireless sensing microsystems plays an important role in the upcoming internet of things (IoT) era. Temperature is one of the most common physical parameters. Consequently, high performance CMOS temperature sensors become an important design element of many microsystems. Apart from that, temperature compensation for other kinds of sensors is also widely employed due to the intrinsic temperature dependence in many commercially available sensors. Due to the application considerations, these systems are usually miniaturized with limited battery storage, and some (e.g. passive RFID) maybe even battery-less for further production/maintenance cost reduction. Consequently, it is challenging to achieve ultra-low power which can be in the order of μW to even nW, while achieving high accuracy without elaborate calibration efforts. Apart from that, good supply immunity is also necessary to ensure accurate sensing under significant supply noise. This seminar will first review the system level requirements of passive RFID, followed by the introduction of the fundamentals and operating principles of CMOS temperature sensors using different sensing devices. The main sources of inaccuracy will be identified, followed by possible circuit/system level solutions to achieve high power/energy efficiencies. Different case studies of state-of-the-art CMOS temperature sensors will also be introduced.

Common-mode rejection ratio (CMRR) is a fundamental consideration in the design of instrumentation amplifiers (IA). This talk studies the CMRR consideration with focus on the enhancement techniques. For AC-coupled IAs, the CMRR is often dominated by the mismatch of passive components, which can be improved by a modified chopping structure and impedance trimming. Theoretically, by cancelling the CM current, the CMRR can be improved structurally. The idea can be realized with a dedicated CM loop which replicates the input CM voltage along with the DM path, eliminating the generation of CM current. Moreover, the input CM impedance is improved simultaneously due to the elimination of CM current, which is typically required by IAs interfacing with high-impedance sensors, e.g., dry-contacted electrodes, accelerometers, etc. Demonstrated IA design examples are discussed.

Power-supply noise (PSN) is a key consideration that determines the performance as well as functionality of ICs, especially for modern SoCs with significantly increased scale, level of integration and driving complexity with sophisticated voltage and power controls. Externally measured PSN is inevitably distorted by packaging, PCB, etc., therefore, on-chip or on-die measurement of PSN is highly demanded with large bandwidth, high accuracy and high frequency resolution, which is extremely challenging. Moreover, clean supply is not available in this scenario. This talk overviews the on-chip PSN analyzer techniques, where the subsampling-based approach is promising due to the relaxed bandwidth constraints. However, the accuracy and frequency resolution are fundamentally determined by the number of averaging points, resulting in long measurement time. Multi-slice architecture, time-based quantizer and compressed sensing techniques are discussed with a 20GHz PSN analyzer design example, where significantly improved measurement accuracy and speed are demonstrated in addition to the system scalability.

Design of integrated circuits under near-/sub-threshold supply voltages is driven by the continued technology scaling as well as the increased demand on energy efficiency. Comparing with digital design that can often be compensated from system level, subthreshold analog design relies more on circuit-level techniques. This talk overviews the state-of-the-art subthreshold analog design techniques. Low-voltage design considerations are discussed along with several 0.1V-0.3V OTA and ADC examples. An evolutionary approach from matured amplifier topologies to inverter-based implementation is presented, which has been exploited and demonstrated in the design of near- and/or sub-threshold amplifiers, regulators, integrators and ΔΣ modulators. The potential of time-domain signaling in low-voltage design is also discussed.

SAR ADCs are coming of age due to the mostly digital implementations where the benefit of advanced CMOS technologies can be generally brought into ADC designs. Time-domain signaling is also promising since the speed and time resolution are both scaling favorable. Therefore, the SAR ADCs with time-based comparator have attracted significant interest in recent years. Nevertheless, comparing with oversampled converters where the unique property of VCO, the first-order noise shaping, has been used to enhance the system, Nyquist converters uses only the bit decision of time-base comparison. This talk introduces the concept of oscillation-cycle information in VCO-based comparators. With rigorous analysis, the number of oscillation cycles (NOC) can be generally exploited as a parallel coarse quantization with a large signal, and/or as a quantitative indication of metastability with a small signal. Moreover, the NOC is inherent and of little cost in hardware, power and area. The demonstrated VCO ADCs exhibit significantly enhanced linearity and robustness, comparing with their voltage-domain counterparts. This talk discusses also a closed-form metastability analysis of VCO-based comparator, introducing the metastability depth as a quantitative measure of metastability.

Facing a growing number of patients with neurological disorders, there are only limited therapeutic pharmacological measures which provide only temporary and mild amelioration of the devastating symptoms of these disorders. The use of electrical stimulation of the brain is a treatment option for patients with severe treatment-resistant disorders. Current deep-brain stimulation (DBS) approaches are hindered by inadequate technology that is low-precision and bulky, power-inefficient, and of limited diagnostic utility. The seminar will discuss a high-precision implantable neurotechnology for closed-loop neuromodulation of functional networks of the human brain. Key features of the technology are: 1) sensing from a high number of channels, 2) sensing concurrent with stimulation for true closed-loop operation, and 3) real-time secure wireless data telemetry. The proposed neurotechnology could revolutionize brain therapies in efficacy, size and cost of medical implants.

Technology scaling is power-limited, so compute energy efficiency improvements have to come from chip and system architectures. Increasing application diversity also argues for a more flexible compute architectures, further emphasizing the need for energy efficient design methods. This includes not just chips, but system solutions and dealing with miniaturization and complexity considerations. This talk will therefore discuss design methods for digital chip and system design, provide a detailed example of fixed-function accelerator architecture study, discuss several chip examples for baseband communications processing, and discuss system integration techniques ranging from next-generation medical implants to next-generation wafer-scale chip packaging. These applications further reveal opportunities in system-level design automation that would help address design productivity and system assembly challenges.

The power generation of transistors drops as we move to higher frequencies. At the same time, the free space propagation loss increases, demanding more radiated power from the system. The loss of passive elements in the circuit increases as well, making functions such as oscillation or radiation even more challenging. In order to boost the limited power, multiple sources need to be coupled together in an array structure. However, the significant loss of the coupling circuitry and phase shifters at mm-wave and terahertz frequencies hinders the implementation of large and efficient radiator and phased arrays. Scalable standing wave array structures are proposed based on efficient low-loss coupling schemes in order to boost the power and operation bandwidth. Furthermore, we present a practical approach to maximize Equivalent Isotropic Radiated Power (EIRP) of the source by optimizing influential parameters of the radiation apparatus. Finally, we demonstrate a new phase shifting method based on combining standing and traveling waves and show how it can achieve significantly higher phase shifting range and bandwidth.  Using all these methods we present coupled-oscillators, scalable radiator arrays, and phased arrays with record beam steering range, tuning range, and output power among relevant published works at mm-wave and terahertz frequencies.

In recent years many new mm-wave applications and standards have been emerging. These systems are mostly a response to the ever-growing demand for higher data speed, higher image resolution, and better sensing systems. The same trajectory to THz and higher frequencies will likely to continue in future for higher performance systems. Therefore, it is vital to understand the limit and capabilities of the fabrication platforms specially when the operating frequencies are getting close to or even surpassing the maximum oscillation frequency (fmax) of the transistors. In this talk we will discuss and present three transistor limits for oscillation frequency, harmonic generation, and power amplification. Using these analyses, we have implemented oscillators and amplifiers with record breaking DC-to-RF efficiency and output power at mm-wave and THz frequencies.

Accurate, stable and wideband mm-wave and terahertz sources prove to be essential for coherent data link, active sensing, and radar. The high frequency of operation creates major challenges for implementing such sources such as low tuning range and output power of voltage controlled oscillators (VCO), small locking range for injection locked frequency dividers, and in general high noise level and power consumption of frequency synthesizers. We present a mode switching technique to significantly increase the tuning range of the VCO’s at 200GHz and above. Moreover, a Colpitts-based active varactor (CAV) and a frequency divider with three-phase injection are proposed to reduce the effective loss of the varactors and increase the tuning range of the VCO combined with the frequency divider at 300GHz. Finally, a frequency lock detector is presented for sub-sampling PLL’s that avoids high-frequency dividers, and results in significantly lower power consumption at mm-wave frequencies. Applying these ideas, we demonstrate record breaking VCO’s and frequency synthesizers operating at 40, 200, and 300GHz.

Thanks to the tremendous advances and success of deep neural networks (DNNs), computer architecture research has been booming and enjoying its "Golden Age" recently: a lot of architectural proposals have been proposed for the accelerated execution of the inference or training of DNNs, especially at the edge. Most of them have common architectural features: i.e., hardware-oriented, reconfigurable, domain-specific, and in/near-memory. This talk will try to provide insights on why they are happening and what are the recent findings by showcasing recent research activities mostly in my group.

Neural interface technologies stand to revolutionize disease care for patients with neurological conditions and in the future, the human experience. Today, implantable neurostimulation devices have seen widespread adoption in the treatment of Parkinson’s disease, OCD, epilepsy, and more. Clinical neurostimulators have few channels and provide simple electrical pulses that are programmed by a doctor in a process that can take months or even years. In this talk I will present WAND: Wireless, Artifact-free Neuromodulation Device, which combines high channel count neural recording with stimulation in a truly closed-loop manner for the first time. This technology, enabled by advances in integrated circuit design, will enable patient-specific therapies that will result in improved outcomes and reduced side effects and pave a path to bidirectional brain-machine interfacing. I will also present recent research in a new class of ultrasound-powered interfaces that has enabled us to scale complete wireless neurosensing and neurostimulation devices to volumes below 1mm³, enabling minimally invasive implantation and safe, chronic use inside the human body.

IC chips are key enablers of densely networked smart society and need to be more compliant to security and safety. The talk will start from Electromagnetic Compatibility (EMC) techniques of IC chips on the safety side, toward EMC aware design, analysis and implementation. Then, the challenges will be discussed about the deployment of EMC techniques in the design of IC chips for the higher level of hardware security. Design and simulation techniques of crypto-based secure IC chips with countermeasures for side-channel attacks will also be discussed.

Interactions of IC chips and packaging structures differentiate the electronic performance of power delivery networks (PDNs) in traditional 2D and advanced 2.5D and 3D technologies. This presentation discusses their impacts on signal integrity (SI), power integrity (PI), electromagnetic compatibility (EMC) and electrostatic discharge protection (ESD), through in-depth Si experiments with in-place noise measurements and full-chip level noise simulations. Test vehicles under study are given in traditional 2D face up and flip chip packaging, 2.5D fan-out wafer level packaging (FOWLP), and 3D chip stacking with through silicon vias (TSVs).

Hardware security, application of modern digital cryptography and authentication technologies for protecting information in electronics, involves analog functionality to avoid physical threats in operation fields. This presentation provides an overview with historical aspects of on-chip physical attack protection circuits and assembly structures for the detection and disablement of malicious attempts on cryptographic devices. Design examples to combat passive and active side channel attacks as well as hardware Trojans are discussed and demonstrated with test vehicles.

Noise coupling in RF system-on-chip integration is studied by on-chip and on-board measurements as well as by concatenated simulations at chip and system levels. Integrated power and substrate noise simulation techniques use chip-package-system board combined circuit models and verify noise coupling in mixed analog-digital integration. Wireless system level simulation evaluates the impacts of coupled RF noises on wireless performance through metrics of throughput and error vector magnitude (EVM). In addition, post-silicon techniques at packaging and assembly stages are potential options to mitigate RF noise coupling problems. The presentation will also include demonstrations with test vehicles.

We have developed a CMOS image sensor with an organic photoconductive film (OPF) laminated on pixel circuits, different from those of a conventional silicon image sensors, in which the organic thin film for photoelectric conversion and the charge storage part for signal charge accumulation are completely independent. In this presentation, we focus on the advantageous features of the OPF image sensor; [1] technology that realizes over 120 dB simultaneous-capture wide dynamic range; [2] global shutter technology achieving high saturation signals per unit square that is 10 dB higher than that of silicon image sensors with the global shutter function, without sacrificing pixel area; [3] RGB-NIR sensor technology capable of controlling NIR sensitivity by simply controlling the voltage applied to the OPF. Moreover, we introduce about 8K4K high resolution sensor technologies with 60fps high frame rate, 450ke- high saturation signals, and the global shutter function at the same time. We believe these features of the OPF image sensor will contribute to leaps in the imaging and sensing fields.

System behavior and performance of power management strongly depend on the implementation on circuit level. This tutorial covers the design of DCDC converter building blocks like power switches, gate drivers and their supply, level shifters, error amplifier as well as control loop and current sensing techniques. Circuits for diagnostics and protection will also be addressed. Increasing switching frequency scales down passive components, but poses a challenge for the design of timing critical circuits. The lecture will highlight trade-offs between speed, efficiency, complexity, voltage and current capabilities, etc.

Efficient conversion of energy is one of the megatrends, enabled by advanced semiconductors and microelectronics. As a wide-band gap material, GaN (gallium nitride) offers a huge potential to reduce the overall power electronics system size and cost. However, parameters such as common-mode transient immunity (CMTI) and minimum parasitic gate loop inductance become more challenging, as they degrade the fast-switching performance. This lecture presents design aspects on system and circuit level related to GaN. The concept of high-voltage energy storing (HVES) enables highly integrated gate driver designs, which can even utilize the parasitic gate loop inductance for a resonant gate drive approach. Monolithic GaN-on-Si integration reduces the gate loop inductance nearly to zero and allows for integration of a full power converter including a fully integrated control loop on a single die. A self-supplied 400V 15W offline buck converter GaN-IC will be discussed with which achieves superior efficiency and power density along with lowest component count. Original analog circuits in GaN are presented such as nmos-only auto-zero comparator and high voltage supply regulator.

Power Management has significant impact on the overall system size and cost of systems-on-chip. Multi-MHz DCDC converters enable highly integrated power management solutions. Automotive and server applications are supplied by nominally 12V with a trend for higher supply voltages towards 48V. Hence, converters with high conversion ratio are required to supply CPUs, MCUs, RAM, etc. This talk addresses the challenges on system and circuit design level for highly integrated, fast switching point-of-load converters, including power stage design, high resolution dead time control and soft-switching.

Power management comprises integrated circuits for highly efficient power supplies and for controlling power switches. These have recently gained tremendous importance in order to make electronic solutions for global growth areas such as renewable energies, autonomous driving and biomedical more compact, more energy-efficient and more reliable. Future applications in the field of machine learning and AI will only be possible with intelligent power management to supply complex processors and sensors. This talk gives an overview at system and circuit level of current and future challenges, along with examples including the topics of automotive, wearables, GaN, and current measurement.

The demand of low-power and high-speed ADC has been escalating in the past decade due to emerging low-power applications with wide bandwidth requirement, including both wireless and wireline systems.   Historically, the ADC in this targeted specification regime has been dominated by Flash topology, where all the level comparisons are accomplished in parallel. However, the associated complexity prevents it from a true low-power solution. More than a decade ago, the asynchronous successive approximation (SAR) architecture was proposed to minimize the overall converter complexity while improving the speed of the SAR search algorithm. The first proof-of-concept silicon prototype in 130nm CMOS achieved the order-of-magnitude improvement in power efficiency.  Since then, this low power ADC architecture has been widely adopted for various power-constraint, high-speed (up to 10s’ GS/s), medium to high resolution applications.  In this talk, we will review the evolution of this ADC architecture, including the recent trend and potential extensions based on asynchronous operation principles, leading to various hybrid ADC architectures.

There are increasing interests in wideband and flexible waveform synthesis in modern communication systems. The key enabler in such a digital transmitter is a high performance digital-to-analog converter (DAC). This has motivated the design community to push the digital-to-analog converter (DAC) towards higher sampling rate (>GS/s) while achieving high dynamic range. Moreover, there is an emerging trend to design a DAC with high output power, i.e. a digital power amplifier (PA). In this talk, I will overview various digital-to-analog architectures and filtering techniques that push the envelope of DAC bandwidth, linearity and/or noise floor. A dual-rate hybrid DAC architecture is one such example. In addition, I will introduce an emerging digital PA architecture that aims for high power efficiency, namely sub-harmonic switching (SHS) PA. Validated by a series of silicon prototypes, the proposed DAC architectures show a promising path for future digital transmitter.

Uniform sampling has been widely adopted in today’s circuit designs, ranging from data converters (ADC and DAC), and discrete-time signal processing (such as switched-capacitor filters). It is a well-developed processing technique that leads to many circuit architectures. However, Nyquist theory does not limit us to processing the samples at a uniform time grid so long as the average sample rate is sufficiently high, i.e., no loss of signal information. Why not sample the analog signal in a non-uniform time grid? What is the benefit by doing so? What is the underlying signal processing implication? In this talk, I will provide a background overview and explore new opportunities in non-uniform sampling (NUS) along with several silicon prototypes (from data converter to RF transceiver) that leverage non-uniform sampling. Thanks to the unique properties of NUS, there are interesting possibilities for future circuit- and system-level architectural innovations.

A phase locked loop (PLL) that uses a digital control loop is becoming a popular architecture for frequency synthesis, typically known as digital PLL or all-digital PLL. The mostly digital nature of such PLL design allows new digital signal processing (DSP) opportunities. In this talk, I will first overview the recent trend of digital PLL design and its design principles. Next, I will describe several emerging techniques applied in this mostly digital architecture to further enhance its performance and robustness. Specifically, one key design objective of a frequency synthesizer is to minimize the spurious tones, as they can degrade the overall jitter performance or cause other unwanted system-level impairments. We will examine the sources of the spurious tone generation and different means to mitigate them. Lastly, we will go over several real PLL design examples that demonstrate low-spur performances.

For many years, a majority of class D audio amplifiers have been switching at a relatively low frequency (several hundreds of KHz). However, there are several drawbacks associated with relatively low switching frequency: 1: Limited loop gain that could bottleneck the linearity of the class D amplifier, especially those delivering high output power. 2: Relatively expensive and large LC filters, which are required to filter out the switching tones to meet the stringent EMI standard for applications such as automotive application. 3: Tricky frequency compensation when the LC filter is incorporated in the amplifiers' feedback loop. Increasing the switching frequency (>2 MHz) can naturally mitigate these issues. However, there are challenges to be addressed. In this lecture, we will discuss design considerations and techniques to achieve high linearity, low EMI, and relatively low idle power with high switching frequency class D amplifiers.

Precision amplifiers are essential blocks for many measurement systems, where offset and flicker noise must be significantly suppressed. Dynamic offset cancellation techniques such as chopping, auto-zeroing, and correlated double sampling are often employed to suppress offset and flicker noise. However, these techniques could introduce some "side-effects" such as noise folding, increased input current, decreased input impedance, intermodulation distortion, etc., which should be addressed properly. In this lecture, an overview of dynamic offset cancellation techniques will be given, followed by the techniques to mitigate the non-idealities introduced by dynamic offset cancellation techniques. Examples of application-specific precision amplifiers will be studied as well.

Millimeter-wave radars for automotive and industrial electronics are increasingly being developed in RFCMOS technologies.  The dense integration of high-performance digital logic enables new capabilities for these systems.  Built-in-self-test circuitry can be used in the field to monitor faults, enabling safety critical applications.  The same circuitry can be reused for calibration to stabilize performance over manufacturing and environmental variations.  In dense coexistence scenarios, side- and in-band information can be used to localize and mitigation interference.  These techniques simultaneously reduce the cost and improve the robustness of mm-wave sensors, with many also being directly applicable to emerging mm-wave communication systems.

Millimeter wave frequency operation offers wide bandwidths, precise localization, and rich material interaction and penetration capability.  Meeting consumer demand for enhanced safety, 77GHz automotive radar is one of the fastest growing features in automotive.  Leveraging the dense integration and fast transistor performance of modern silicon processes, emerging MMICs are delivering higher performance in a smaller form factor and are also extending the mm-wave capabilities to other sensing markets, including intelligent infrastructure, robotic navigation, high accuracy displacement and motion sensing, and human interaction.  This talk will cover these application trends and how they are enabled by emerging radar ICs.

The Internet of Things (IoT) market requires radios that operate with very low average power consumption to enable battery life measured in years, or even battery-free operation.   Standards used in IoT applications, such as Bluetooth Low Energy, also have relaxed performance requirements allowing the radio to be optimized for low power operation.   This tutorial will introduce several types oscillators used in these IoT radios, explaining how the low power system level requirements influence the oscillator architecture, design, and performance targets.   Design examples and power/accuracy tradeoffs will be described for sleep timers, RF synthesizer reference clocks and high frequency VCOs, and system clocks used for the MCU and peripherals.   At the end of the tutorial, attendees will have a solid overview of the many types of oscillators present in a typical IoT wireless node and understand design tradeoffs for each.

The first crystal oscillator was designed approximately 100 years ago, and today there are few electronic devices without at least one crystal oscillator to generate an accurate clock reference.   Despite being ubiquitous, crystal oscillators have drawbacks, including cost, large size, degraded frequency stability at temperature extremes, and sensitivity to shock and vibration.  In the quest for further reducing the footprint of electronic systems to enable new applications, it is desirable have a high stability resonator that can be integrated into an SoC, while ideally also reducing some of the drawbacks of crystals.    Bulk acoustic wave resonators (BAW) are one type of device that has been suggested for this application, with the first BAW oscillator built 40 years ago.   The first prototypes suffered from inaccurate frequency and relatively large size.  Since then, many advances have been made, and BAW oscillators are now a commercial reality.   This presentation will cover the physics of BAW resonators, including frequency selection and passive temperature compensation, and circuits design considerations, such as oscillator topologies, frequency tunability, jitter reduction, and active temperature compensation.   Finally, system level advantages will be presented, including improved security and resistance to tampering.

Over the last decade, low power wide area networks have experienced significant growth, filling a market need for industrial applications that require battery operated remote sensors to send small amounts of data over distances of >1km.   This tutorial will cover the various standards and protocols both used currently and in development for this market, such as NB-IoT, LoRaWAN, MIoTy, Wi-SUN/802.15.4, and SigFox.   The LPWAN standards will be compared in terms of achievable sensitivity, data rate, network topology, network density, link budget, data rates, security and radio power consumption.    Each of these standards places different requirements on the RF circuits required to meet the design goals.   The tutorial will provide attendees with a solid overview of the current IoT low power wide area network landscape and the design challenges involved, including an overview of relevant radio architectures.    

The first commercial Bluetooth device was launched in 1999.   Analysis of nearly 100 datasheets and published IEEE conference and journal papers shows that since 1999, active power consumption for Bluetooth/Bluetooth Low Energy radios has reduced by 20x, while sensitivity has improved by 15dB.  This talk will explore which innovations have made this possible, and to what degree, including updates to the Bluetooth standard and advances in silicon process technology, radio architectures, and circuit design.   Many of these power consumption and sensitivity improvements are not applicable to just Bluetooth products but can also carry over into other low power wireless connectivity protocols.   This talk will discuss what power consumption trends we can we expect in the future and what challenges remain to be solved.

The unprecedented growth in Deep Neural Networks (DNN) model size has resulted into a massive amount of data movement from off-chip memory to on-chip processing cores in modern Machine Learning (ML) accelerators. Compute-In-Memory (CIM) designs performing DNN computations within memory arrays are being explored to mitigate this ‘Memory Wall’ bottleneck of latency and energy overheads. Multiple memory technologies with unique attributes are being explored for enabling energy efficient CIM designs.

In this talk, I will present trends in recent CIM designs and highlight key principles utilized for performing multi-bit Multiply-Accumulate (MAC) computations using both analog and digitally-intensive approaches. The design trade-offs among bit-precision, throughput, energy efficiency, data converter overheads, and computational accuracies will be discussed. In addition, the prospects of compute-in-memory designs for applications beyond DNNs will also be presented.

Static Random Access Memory  (SRAM) technology is the enabler of advanced logic technology node scaling and has significant implications on continuation of Moore’s law. Embedded SRAM capacity is growing across all product segments ranging from battery powered SoCs (IoT edge devices), to high performance ASICs (FPGA, Modems, Microprocessors) to emerging machine learning accelerators (GPU, TPU, NPU). In advanced FinFET technologies, the 2-dimensional scaling is becoming increasingly challenging degrading the SRAM scaling metrics (such as Vmin, bitcell area, array efficiency). This effect is further exacerbated in SRAMs due to the fundamental read vs. write operation conflict as well as worsened interconnect parasitics affecting critical wordline and bitline signal performance.

In this talk, I will describe recent trends in high performance SRAM designs in modern FinFET technologies and discuss various process, device, and circuit innovations enabling continued SRAM scaling. I will also present an overview of other logic technology compatible embedded memories such as ROMs, PROMs, Register files. In addition, various technology scaling boosters such as buried rail technology for sub-5nm FinFETs, 3-D integration (split-3D, monolithic 3D) will also be presented.

The continuous growth in computing technology emerges various advanced information services today. The information managed in such services is becoming increasingly critical and hence valuable for malicious attackers. In order to steal, destroy, or manipulate such information in a cyber domain, the attackers exploit security holes in a physical domain computing entity i.e. IC hardware. This so-called cyber-physical attacks are currently one of the most serious security threats in realizing future advanced information society where the information security is the-root-of-trust of all the critical services such as autonomous driving, drone guard, and robot nursing. This lecture will cover several key countermeasures namely integrated security interface against the cyber-physical attacks, including 1) power/EM side-channel, 2) EM/laser fault-injection, 3) chip-package-board hardware counterfeiting, 4) sensor spoofing attacks, and 5) future perspectives on the information security in the next-generation society.

Metal interconnections on a chip are utilized not only for wiring but also for a part of functional circuits, such as a well-known passive capacitor and inductor. Today with the technology scaling, we have plenty of metal resources available on chip, providing great flexibility to create fine and delicate highly-integrated metal structures with tremendous high-performance scaled transistors. By aggressively exploiting EM field generated around the metal structures and controlling its field shape by active transistor circuits, the metal interconnections can emerge active smart functionality. This so-called smart metal passive is one of the key solutions to overcome scaling limit based on the conventional Moore’s Law. This lecture will introduce several design examples of the smart metal passives for emerging More-than-Moore applications, including 1) near-field wireless interconnection for 3D ICs, 2) sealed permanent memory by metal nano-dot structure, 3) high-resolution touch sensor for direct electric brush art, 4) physical attack sensor for hardware security, and 5) future direction of next-generation computing system featuring the smart metal passive.

For at least 3 decades techno-polemicists have been saying that analog circuits are “dead”, even as the field has exploded both commercially and academically.   What is definitely true, however, is that analog circuits have changed, as digital computation and analog-to-digital converters have improved by leaps and bounds, pushing many traditionally analog problems into the digital, and even software domain.  A number of problems, however, remain beyond the reach of purely digital solutions.  These problems are generally characterized by either extremely constrained power (and so size) budgets, by very high frequency operation, or by very high dynamic range requirements.  At the same time, such circuits must be designed with a much more algorithm-aware mindset, as they rarely exist in a computation-free environment.  In this talk I will discuss two examples of such circuits.  The first addresses the duplex problem in software defined radios.  Here a single transceiver chip has been designed to detect weak RF signals while simultaneously transmitting ~1 trillion times more powerful signals on the same RF port, and to do so at arbitrary (software defined) RF frequencies.  Accomplishing this requires a marriage of novel RF circuitry with control and optimization algorithms.   The second example operates at the other extreme of speed and power: we have recently developed a tiny (50mm x 250mm) neural implant, able to measure and transduce electrophysiological signals from neurons and transmit them wirelessly. These microscale optoelectronically transduced electrodes (MOTEs) can be entirely powered by light (from a 2-photon imaging setup, for example), at levels safe for the brain, while reporting the entire electrophysiological spectrum (~10Hz-10kHz) at ~10mVRMS noise levels through a train of encoded light pulses. 

The RF spectrum used for wireless communications is growing increasingly crowded and dynamic creating challenges   One way to mitigate this crowding is to allow radios to be much more flexible in how they access spectrum, so that they can opportunistically use available spectrum across time and space.  A primary bottleneck to such transceivers is their ability to withstand interference on their receivers, both from other users and from their own transmitters.  Here I will discuss several concepts we have developed for highly integrated, flexible, interference-tolerant radio transceivers.  The first concept is the N-phase passive mixer (or “N-path filter”); known for decades, the advent of deep-submicron CMOS has enabled such N-path passive mixers and filters to be scaled to GHz frequencies with extremely high out-of-band linearity and surprisingly good in-band noise. I will briefly review the basic operation and properties of such circuits, as well as some of our recent work on techniques for mapping N-path filters to mm-wave frequencies.  Many of these techniques will then be applied to the second concept, the distributed duplexing transceiver, which combines N-path techniques with a transmitter topology akin to a distributed amplifier to allow frequency flexible FDD without off-chip diplexers.  Finally, I will briefly describe other quasi-distributed topologies for receivers that provide an additional degree of tolerance to interference when interacting with phase noise and other LO imperfections.

Light can be employed in integrated circuits in a variety of ways to enable surprising new capabilities that go well beyond traditional CMOS systems-on-chip.  Here I will discuss three non-standard ways that light can be used with CMOS circuits to enable biological sensing.  The first is a set of diffractive techniques to allow enable “angle sensitive pixels” and so enable lensed and lensless 3-D microscopy, as well as a variety of other interesting imaging capabilities.  The second is an alternate way to use angle sensitive sensors to directly digitize angle of incidence. When combined with integrated solar cells and simple signal processing and data-logging, this enables mm-scale autonomous flight-heading trackers to reconstruct flight paths of bees.  Finally, integrating micro-LEDs and photovoltaics on 100um-scale autonomous sensors allows wireless power and data transfer through tissue.   This capability enables truly dust-scale sensors for detecting electrophysiological signals, and potentially many other biologically relevant signals.  Taken together these results illuminate a variety of ways that codesign of optical and electronic functions in standard CMOS can open up valuable new capabilities for integrated circuits. 

In this presentation I will discuss N-phase passive mixers (and their close relative the “N-path filter”) as applied to interference tolerant radio receivers.  Although known for decades, the advent of deep-submicron CMOS has enabled N-path passive mixers and filters to be scaled to GHz frequencies with surprisingly good performance in both noise and linearity. I will briefly review the basic operation and properties of such circuits, and provide an intuitive analysis of the circuit and transistor properties that limit their performance, including insights into their response to phase noise.  Such N-path mixers, as originally conceived, and as implemented in the sub-10GHz regime, however, place requirements on their Local Oscillator waveforms that are ill-suited to the higher frequency (e.g. mm-wave) operation required for newer standards such as 5G. I will therefore also introduce a second set of design techniques and analytical results enable similar function at much higher frequencies

Fine grained spatiotemporal power management in digital processors and SoCs require embedded voltage regulators that are compact, energy-efficient, and able to operate over a large dynamic range. Linear regulators, including low dropout (LDO) regulators are the popular choice for on-die voltage regulation. Although analog LDOs have been used in supply sensitive load circuits over the years, there has been a recent resurgence in research and development of digitally assisted and all-digital LDOs targeted for digital load circuits. In some of these topologies, traditional design metrics such as power supply rejection, line and load regulation are often traded-off for higher energy efficiency, high performance under large current and voltage transients, as well as wide dynamic range of operation. In particular, the ability of digital topologies to regulate with ultra-low dropout voltages and down to the near threshold voltage (NTV) region have garnered significant interest. In this talk I will discuss recent advances in both circuit topologies and the corresponding control theoretical models of such LDOs. Emerging circuit topologies representing both all-digital and digitally assisted analog LDOs will be discussed. In the last part of the talk we will explore circuit topologies that unify voltage regulation and clocking circuits to provide and allow designers to reduce voltage guard-bands in digital circuits.

As we march towards the age of “ubiquitous intelligence”, we note that AI and Machine learning are progressively moving from the Cloud to the Edge devices. The success of Edge-AI is pivoted on innovative circuits and hardware that can enable inference and limited learning, in hardware-constrained ultra-low-power (uW to mW) systems – an area of active research. In this talk, I will discuss the promises and outlook of Edge-AI and their applications in Autonomous Systems; and elaborate on some of our recent work on enabling such systems in sensor nodes and robotics. While some of these systems extend our understanding of statistical machine learning, a large class of circuits and systems are inspired by the information representation in the brain. I will talk about the design of such circuits and systems with an emphasis on the impact of mixed-signal circuits, near-memory and in-memory compute architectures, non-CMOS (RRAM-based) compute macros, as well as algorithm-hardware co-design to realize the most energy-efficient Edge-AI ASICs for the next generation of smart and autonomous systems.

Since late 2000’s, SAR ADCs have become one of the most popular ADC architectures showing not only excellent power efficiency but also competitive conversion speed owing to the digital-friendly compact structure and architectural evolution in deep submicron technologies. Being utilized as sub building blocks, SAR ADCs could also enhance the performance of other types of ADCs such as pipelined, delta-sigma, and even flash ADCs. This talk discusses how SAR ADCs could have improved the ADC performance with various ADC architectural modification.

While SAR ADCs have become one of the most popular ADC architectures during the past decade owing to its compactness and power-efficiency in advanced CMOS processes, their limited conversion rate still remains as a major design bottleneck even with time interleaving (TI), especially in implementing high-resolution. Meanwhile, pipelined ADCs have been evolved to circumvent the opamp-based power-hungry residue generation. Often with SAR ADCs as sub-stages, recently, pipelined ADCs could achieve both high conversion rate and power efficiency. As pipelining also alleviates the calibration burden of channel-mismatch in TI ADCs owing to the reduced number of high-speed channels, this architecture needs to be improved continuously. Based on this perspective, this talk aims to provide knowledge on pipelined ADCs and recent remarkable design examples.

For over half a century, ICs have been designed and productized to advance computing performance and efficiency. Perform careful, detailed, and creative circuit design to build computing systems. With the impressive strides enabled by computing, can we now integrate computing to enhance circuit and system capabilities? If so, under which conditions and to what extent? Are there pitfalls? In this talk, we present an overview of ways and degrees in which computing can augment circuit implementations across diverse applications. These include enhancing the density and capability of neural interfaces, improving hardware security, and accelerating PLL lock time. We then examine the use of run-time computing in two applications: design of integrated voltage regulators and autonomous tracking of minimum energy point (MEP) operation. The different ways in which computing can replace or augment traditionally circuit-based solutions will be illustrated with test chip demonstrations of (1) a computationally enhanced Digital Low Dropout Regulator with 2.8-cycle mean recovery time and autonomous PVT tuning, (2) a model predictive buck regulator capable of time-optimal control under random loading conditions, and (3) autonomous MEP tracking to realize ultra-low power systems under performance guarantees. Finally, we highlight the advantages of such approaches, their current limitations, and potential for future advances.

Energy efficiency remains a key concern in modern SoCs. Despite tremendous advances in packaging and power delivery, the margins required to withstand supply voltage noise still play a dominant role in dictating SoC energy efficiency. Starting from early efforts that injected charge into the supply, the field has evolved toward instruction throttling and adaptive clocking which have become widely adopted. Even so, there remains significant room for further margin reduction. In this talk, we briefly introduce the problem of supply noise and examine several adaptive clocking techniques that have been adopted over the years to address this challenge. We examine their existing limitations to motivate the design of several recent adaptive clocking innovations that unify voltage regulation and clock generation into a single entity. In particular, the talk will focus on the Unified Clock and Power (UniCaP) architecture. The effectiveness of this technology and its enabling capabilities will be discussed through multiple test-chip demonstrations and measurements. These include a performance-regulated 65nm Cortex M0 processor which achieves 98% voltage margin reduction, a frequency-locked sub-threshold processor that demonstrates 90% margin reduction while tracking both temperature variation and voltage noise, and a more recent SIMO implementation that draws 58% lower power than a conventional iso-performance implementation. Finally, we discuss some UniCaP limitations that inform both its existing usability and future directions.

With datacenters mushrooming around each other to provide the necessary bandwidth for our computing and communication needs, the need to interconnect them with optical fibers at low cost and high energy efficiency has significantly increased. Coherent silicon photonic links bear the promise to satisfy that demand at an unprecedented scale, integration, and (low) cost. In this talk, I will briefly introduce silicon photonics, describe our recent work on silicon photonics 16-QAM coherent links operating at 0.5Tb/s, and comment on some of the subsequent research opportunities in coherent silicon photonics.

What is a good frequency synthesizer? A survey of CMOS phase-locked loops (PLLs) over the last two decades shows that the overall performance of PLL-based frequency synthesizers is bounded by a tradeoff between noise, area, and power consumption. Analog PLLs with a charge-pump integrator (Type-II) suffer from charge-pump and detector noise, and are area- and power-hungry. All-digital PLLs are compact and friendly to technology scaling but limited in noise performance under a restrained power budget. 

The simplest frequency synthesizer is one utilizing the least noise-inducing components in the loop. The recipe to design the lowest noise synthesizer is simple: (1) Choose the VCO with the lowest phase noise. (2) Reduce its low-offset phase noise by locking it to the cleanest frequency reference with a large loop bandwidth. (3) Eliminate/suppress other noise sources. Such a loop can be realized as Type-I, without an integrator in the loop filter. Such synthesizers thus comprise subsampling Type-I PLLs and injection-locked (Type-I) PLLs. They achieve low noise performance in a compact footprint and low power budget. And the limitations of classical Type-I, subsampling, and injection-locked topologies can be remedied using two classical design philosophies - 1) a simple design is often a good design, and 2) use digital CMOS where it is good at. Such digitally-assisted analog synthesizers include the best of both worlds.

In-band Simultaneous Full-Duplex (FD) radio communication, where the transmitter and the receiver operate on the same frequency band at the same time, has been explored as a means to increase the throughput in the last decade. The hurdle in achieving FD is the self-interference (SI) from the transmitter that is several orders of magnitude stronger than the desired signal at the RX. For mobile applications, SI cancellation circuits should be low-power, linear, tunable, low-noise, fully monolithic with a compact form factor, and implemented at the radio frequency front-end. I will describe the challenges in designing an FD single-chip radio for WiFi/ cellular applications, give an overview of the state-of-the-art, and present our work to achieve large delay/broadband cancellation. I will then describe the outstanding challenges toward FD deployment for WiFi/cellular applications. I will also present other wireless applications where FD promises a significant performance improvement.

The devices in the arsenal of a CMOS designer include resistors, capacitors, inductors, and transistors. What happens when we add light to that? With an ability to move the information between electrons and photons, many new opportunities and applications will emerge. In the last five years, silicon photonics - where light is guided in a silicon waveguide on a CMOS SOI process, has already had a significant impact in the field of high-speed transceivers for data communications. 

Which applications will become mainstream in the next 5-10 years? Sensing? Computing? RF & Microwave? Quantum? What will be next in communications? 

And how can we easily add photonics to the arsenal of the CMOS designer and make its adoption seamless? I will attempt to answer some of these questions in this talk. I will also highlight the opportunities that lie ahead for a CMOS designer in adopting this technology - now ready to be deployed.

The sampling kT/C noise is traditionally deemed as a fundamental SNR limit for Nyquist-rate ADCs. To suppress it, the only option is to increase C. Nevertheless, this leads to significant challenges for the ADC input driver and the reference buffer. In fact, the ADC driver and reference buffer are the system bottleneck nowadays. Their power, area, and design complexity can be an order of magnitude higher than the ADC core. Since the root cause of this challenge is the large C, it is highly desirable to break this seemingly fundamental tradeoff between the capacitor size and the kT/C noise. This talk will introduce two techniques that can significantly reduce the capacitor size but without incurring large kT/C noise penalty. The first technique is to operate a SAR ADC in the continuous time to completely avoid the need for the sampling operation. The second is to cancel the kT/C noise using a novel two-step sampling operation. Both techniques can achieve high resolution with orders of magnitude reduction in the capacitance size, thereby substantially relaxing the requirement for the ADC input driver and reference buffer.

Conventional sensor front-end designs all follow the Nyquist theorem that the data acquisition rate must be at least twice the signal bandwidth. Nevertheless, it is not an efficient way to capture a sparse signal, for its information rate can be much lower than suggested by its bandwidth. In fact, many natural signals are sparse including audio, image, and biological signals. Compressive sensing (CS) is a technique that takes advantage of the natural signal’s sparsity and allows the signal to be precisely captured with far fewer measurements than the Nyquist rate. Thus, it opens up a new door to reduce the sensor power. This talk discusses the opportunities and challenges in applying CS techniques to sensor front-end design. Focus will be given on how to develop a hardware-efficient circuit realization for CS. We will cover both single- and multi-channel CS architectures for audio and imager applications. 

This talk introduces a new type of dynamic amplifier, the floating inverter amplifier (FIA). FIA enables current reuse and dynamic biasing, thus achieving excellent energy efficiency. It provides robust operation against process, voltage, and temperature (PVT) variations. Moreover, its output common-mode voltage is well controlled without the need for an explicit common-mode feedback circuit. Two example applications will be described: 1) by performing pre-amplification for the comparator, it enables the most energy-efficient comparator reported to date; 2) two FIAs are cascaded to realize the world’s first high-performance closed-loop dynamic amplifier, which offers high resolution, high energy efficiency, and PVT robustness simultaneously. It makes possible the first fully dynamic noise-shaping SAR ADC with sharp noise transfer function and no calibration.

SAR is widely used for medium resolution applications due to its simplicity, scaling compatibility, and low-power consumption. However, its power efficiency degrades as the resolution increases due to its tight requirement on the comparator noise and the exponentially growing capacitor DAC array. By contrast, DS ADC is a popular architecture for high-resolution applications. Taking advantage of noise shaping, it can achieve high resolution with a low-resolution quantizer and DAC. However, it typically requires the use of op-amps that are power hungry and scaling unfriendly. This talk will present latest hybrid ADCs that aim to combine the merits of SAR and DS while simultaneously obviating their drawbacks. After providing a high-level review of published works, this talk will take a deep dive into two interesting noise-shaping SAR ADC architectures. The first one uses fully passive switched-capacitor filter to achieve 2nd-order noise shaping. It is fully dynamic and can be easily duty cycled. In addition, it is robust and calibration free. Thus, it is well suited for low-power sensor applications. The second one adopts an error-feedback structure, which simplifies the filter design. It consumes very low power by using a dynamic amplifier and address its process, voltage, and temperature (PVT) sensitivity via a fast-convergence background calibration loop.