The demand of low-power and high-speed ADC has been escalating in the past decade due to emerging low-power applications with wide bandwidth requirement, including both wireless and wireline systems.   Historically, the ADC in this targeted specification regime has been dominated by Flash topology, where all the level comparisons are accomplished in parallel. However, the associated complexity prevents it from a true low-power solution. More than a decade ago, the asynchronous successive approximation (SAR) architecture was proposed to minimize the overall converter complexity while improving the speed of the SAR search algorithm. The first proof-of-concept silicon prototype in 130nm CMOS achieved the order-of-magnitude improvement in power efficiency.  Since then, this low power ADC architecture has been widely adopted for various power-constraint, high-speed (up to 10s’ GS/s), medium to high resolution applications.  In this talk, we will review the evolution of this ADC architecture, including the recent trend and potential extensions based on asynchronous operation principles, leading to various hybrid ADC architectures.

There are increasing interests in wideband and flexible waveform synthesis in modern communication systems. The key enabler in such a digital transmitter is a high performance digital-to-analog converter (DAC). This has motivated the design community to push the digital-to-analog converter (DAC) towards higher sampling rate (>GS/s) while achieving high dynamic range. Moreover, there is an emerging trend to design a DAC with high output power, i.e. a digital power amplifier (PA). In this talk, I will overview various digital-to-analog architectures and filtering techniques that push the envelope of DAC bandwidth, linearity and/or noise floor. A dual-rate hybrid DAC architecture is one such example. In addition, I will introduce an emerging digital PA architecture that aims for high power efficiency, namely sub-harmonic switching (SHS) PA. Validated by a series of silicon prototypes, the proposed DAC architectures show a promising path for future digital transmitter.

Uniform sampling has been widely adopted in today’s circuit designs, ranging from data converters (ADC and DAC), and discrete-time signal processing (such as switched-capacitor filters). It is a well-developed processing technique that leads to many circuit architectures. However, Nyquist theory does not limit us to processing the samples at a uniform time grid so long as the average sample rate is sufficiently high, i.e., no loss of signal information. Why not sample the analog signal in a non-uniform time grid? What is the benefit by doing so? What is the underlying signal processing implication? In this talk, I will provide a background overview and explore new opportunities in non-uniform sampling (NUS) along with several silicon prototypes (from data converter to RF transceiver) that leverage non-uniform sampling. Thanks to the unique properties of NUS, there are interesting possibilities for future circuit- and system-level architectural innovations.

A phase locked loop (PLL) that uses a digital control loop is becoming a popular architecture for frequency synthesis, typically known as digital PLL or all-digital PLL. The mostly digital nature of such PLL design allows new digital signal processing (DSP) opportunities. In this talk, I will first overview the recent trend of digital PLL design and its design principles. Next, I will describe several emerging techniques applied in this mostly digital architecture to further enhance its performance and robustness. Specifically, one key design objective of a frequency synthesizer is to minimize the spurious tones, as they can degrade the overall jitter performance or cause other unwanted system-level impairments. We will examine the sources of the spurious tone generation and different means to mitigate them. Lastly, we will go over several real PLL design examples that demonstrate low-spur performances.

For many years, a majority of class D audio amplifiers have been switching at a relatively low frequency (several hundreds of KHz). However, there are several drawbacks associated with relatively low switching frequency: 1: Limited loop gain that could bottleneck the linearity of the class D amplifier, especially those delivering high output power. 2: Relatively expensive and large LC filters, which are required to filter out the switching tones to meet the stringent EMI standard for applications such as automotive application. 3: Tricky frequency compensation when the LC filter is incorporated in the amplifiers' feedback loop. Increasing the switching frequency (>2 MHz) can naturally mitigate these issues. However, there are challenges to be addressed. In this lecture, we will discuss design considerations and techniques to achieve high linearity, low EMI, and relatively low idle power with high switching frequency class D amplifiers.

Precision amplifiers are essential blocks for many measurement systems, where offset and flicker noise must be significantly suppressed. Dynamic offset cancellation techniques such as chopping, auto-zeroing, and correlated double sampling are often employed to suppress offset and flicker noise. However, these techniques could introduce some "side-effects" such as noise folding, increased input current, decreased input impedance, intermodulation distortion, etc., which should be addressed properly. In this lecture, an overview of dynamic offset cancellation techniques will be given, followed by the techniques to mitigate the non-idealities introduced by dynamic offset cancellation techniques. Examples of application-specific precision amplifiers will be studied as well.

Millimeter-wave radars for automotive and industrial electronics are increasingly being developed in RFCMOS technologies.  The dense integration of high-performance digital logic enables new capabilities for these systems.  Built-in-self-test circuitry can be used in the field to monitor faults, enabling safety critical applications.  The same circuitry can be reused for calibration to stabilize performance over manufacturing and environmental variations.  In dense coexistence scenarios, side- and in-band information can be used to localize and mitigation interference.  These techniques simultaneously reduce the cost and improve the robustness of mm-wave sensors, with many also being directly applicable to emerging mm-wave communication systems.

Millimeter wave frequency operation offers wide bandwidths, precise localization, and rich material interaction and penetration capability.  Meeting consumer demand for enhanced safety, 77GHz automotive radar is one of the fastest growing features in automotive.  Leveraging the dense integration and fast transistor performance of modern silicon processes, emerging MMICs are delivering higher performance in a smaller form factor and are also extending the mm-wave capabilities to other sensing markets, including intelligent infrastructure, robotic navigation, high accuracy displacement and motion sensing, and human interaction.  This talk will cover these application trends and how they are enabled by emerging radar ICs.

The Internet of Things (IoT) market requires radios that operate with very low average power consumption to enable battery life measured in years, or even battery-free operation.   Standards used in IoT applications, such as Bluetooth Low Energy, also have relaxed performance requirements allowing the radio to be optimized for low power operation.   This tutorial will introduce several types oscillators used in these IoT radios, explaining how the low power system level requirements influence the oscillator architecture, design, and performance targets.   Design examples and power/accuracy tradeoffs will be described for sleep timers, RF synthesizer reference clocks and high frequency VCOs, and system clocks used for the MCU and peripherals.   At the end of the tutorial, attendees will have a solid overview of the many types of oscillators present in a typical IoT wireless node and understand design tradeoffs for each.

The first crystal oscillator was designed approximately 100 years ago, and today there are few electronic devices without at least one crystal oscillator to generate an accurate clock reference.   Despite being ubiquitous, crystal oscillators have drawbacks, including cost, large size, degraded frequency stability at temperature extremes, and sensitivity to shock and vibration.  In the quest for further reducing the footprint of electronic systems to enable new applications, it is desirable have a high stability resonator that can be integrated into an SoC, while ideally also reducing some of the drawbacks of crystals.    Bulk acoustic wave resonators (BAW) are one type of device that has been suggested for this application, with the first BAW oscillator built 40 years ago.   The first prototypes suffered from inaccurate frequency and relatively large size.  Since then, many advances have been made, and BAW oscillators are now a commercial reality.   This presentation will cover the physics of BAW resonators, including frequency selection and passive temperature compensation, and circuits design considerations, such as oscillator topologies, frequency tunability, jitter reduction, and active temperature compensation.   Finally, system level advantages will be presented, including improved security and resistance to tampering.

Over the last decade, low power wide area networks have experienced significant growth, filling a market need for industrial applications that require battery operated remote sensors to send small amounts of data over distances of >1km.   This tutorial will cover the various standards and protocols both used currently and in development for this market, such as NB-IoT, LoRaWAN, MIoTy, Wi-SUN/802.15.4, and SigFox.   The LPWAN standards will be compared in terms of achievable sensitivity, data rate, network topology, network density, link budget, data rates, security and radio power consumption.    Each of these standards places different requirements on the RF circuits required to meet the design goals.   The tutorial will provide attendees with a solid overview of the current IoT low power wide area network landscape and the design challenges involved, including an overview of relevant radio architectures.    

The first commercial Bluetooth device was launched in 1999.   Analysis of nearly 100 datasheets and published IEEE conference and journal papers shows that since 1999, active power consumption for Bluetooth/Bluetooth Low Energy radios has reduced by 20x, while sensitivity has improved by 15dB.  This talk will explore which innovations have made this possible, and to what degree, including updates to the Bluetooth standard and advances in silicon process technology, radio architectures, and circuit design.   Many of these power consumption and sensitivity improvements are not applicable to just Bluetooth products but can also carry over into other low power wireless connectivity protocols.   This talk will discuss what power consumption trends we can we expect in the future and what challenges remain to be solved.

The unprecedented growth in Deep Neural Networks (DNN) model size has resulted into a massive amount of data movement from off-chip memory to on-chip processing cores in modern Machine Learning (ML) accelerators. Compute-In-Memory (CIM) designs performing DNN computations within memory arrays are being explored to mitigate this ‘Memory Wall’ bottleneck of latency and energy overheads. Multiple memory technologies with unique attributes are being explored for enabling energy efficient CIM designs.

In this talk, I will present trends in recent CIM designs and highlight key principles utilized for performing multi-bit Multiply-Accumulate (MAC) computations using both analog and digitally-intensive approaches. The design trade-offs among bit-precision, throughput, energy efficiency, data converter overheads, and computational accuracies will be discussed. In addition, the prospects of compute-in-memory designs for applications beyond DNNs will also be presented.

Static Random Access Memory  (SRAM) technology is the enabler of advanced logic technology node scaling and has significant implications on continuation of Moore’s law. Embedded SRAM capacity is growing across all product segments ranging from battery powered SoCs (IoT edge devices), to high performance ASICs (FPGA, Modems, Microprocessors) to emerging machine learning accelerators (GPU, TPU, NPU). In advanced FinFET technologies, the 2-dimensional scaling is becoming increasingly challenging degrading the SRAM scaling metrics (such as Vmin, bitcell area, array efficiency). This effect is further exacerbated in SRAMs due to the fundamental read vs. write operation conflict as well as worsened interconnect parasitics affecting critical wordline and bitline signal performance.

In this talk, I will describe recent trends in high performance SRAM designs in modern FinFET technologies and discuss various process, device, and circuit innovations enabling continued SRAM scaling. I will also present an overview of other logic technology compatible embedded memories such as ROMs, PROMs, Register files. In addition, various technology scaling boosters such as buried rail technology for sub-5nm FinFETs, 3-D integration (split-3D, monolithic 3D) will also be presented.

The continuous growth in computing technology emerges various advanced information services today. The information managed in such services is becoming increasingly critical and hence valuable for malicious attackers. In order to steal, destroy, or manipulate such information in a cyber domain, the attackers exploit security holes in a physical domain computing entity i.e. IC hardware. This so-called cyber-physical attacks are currently one of the most serious security threats in realizing future advanced information society where the information security is the-root-of-trust of all the critical services such as autonomous driving, drone guard, and robot nursing. This lecture will cover several key countermeasures namely integrated security interface against the cyber-physical attacks, including 1) power/EM side-channel, 2) EM/laser fault-injection, 3) chip-package-board hardware counterfeiting, 4) sensor spoofing attacks, and 5) future perspectives on the information security in the next-generation society.

Metal interconnections on a chip are utilized not only for wiring but also for a part of functional circuits, such as a well-known passive capacitor and inductor. Today with the technology scaling, we have plenty of metal resources available on chip, providing great flexibility to create fine and delicate highly-integrated metal structures with tremendous high-performance scaled transistors. By aggressively exploiting EM field generated around the metal structures and controlling its field shape by active transistor circuits, the metal interconnections can emerge active smart functionality. This so-called smart metal passive is one of the key solutions to overcome scaling limit based on the conventional Moore’s Law. This lecture will introduce several design examples of the smart metal passives for emerging More-than-Moore applications, including 1) near-field wireless interconnection for 3D ICs, 2) sealed permanent memory by metal nano-dot structure, 3) high-resolution touch sensor for direct electric brush art, 4) physical attack sensor for hardware security, and 5) future direction of next-generation computing system featuring the smart metal passive.

For at least 3 decades techno-polemicists have been saying that analog circuits are “dead”, even as the field has exploded both commercially and academically.   What is definitely true, however, is that analog circuits have changed, as digital computation and analog-to-digital converters have improved by leaps and bounds, pushing many traditionally analog problems into the digital, and even software domain.  A number of problems, however, remain beyond the reach of purely digital solutions.  These problems are generally characterized by either extremely constrained power (and so size) budgets, by very high frequency operation, or by very high dynamic range requirements.  At the same time, such circuits must be designed with a much more algorithm-aware mindset, as they rarely exist in a computation-free environment.  In this talk I will discuss two examples of such circuits.  The first addresses the duplex problem in software defined radios.  Here a single transceiver chip has been designed to detect weak RF signals while simultaneously transmitting ~1 trillion times more powerful signals on the same RF port, and to do so at arbitrary (software defined) RF frequencies.  Accomplishing this requires a marriage of novel RF circuitry with control and optimization algorithms.   The second example operates at the other extreme of speed and power: we have recently developed a tiny (50mm x 250mm) neural implant, able to measure and transduce electrophysiological signals from neurons and transmit them wirelessly. These microscale optoelectronically transduced electrodes (MOTEs) can be entirely powered by light (from a 2-photon imaging setup, for example), at levels safe for the brain, while reporting the entire electrophysiological spectrum (~10Hz-10kHz) at ~10mVRMS noise levels through a train of encoded light pulses. 

The RF spectrum used for wireless communications is growing increasingly crowded and dynamic creating challenges   One way to mitigate this crowding is to allow radios to be much more flexible in how they access spectrum, so that they can opportunistically use available spectrum across time and space.  A primary bottleneck to such transceivers is their ability to withstand interference on their receivers, both from other users and from their own transmitters.  Here I will discuss several concepts we have developed for highly integrated, flexible, interference-tolerant radio transceivers.  The first concept is the N-phase passive mixer (or “N-path filter”); known for decades, the advent of deep-submicron CMOS has enabled such N-path passive mixers and filters to be scaled to GHz frequencies with extremely high out-of-band linearity and surprisingly good in-band noise. I will briefly review the basic operation and properties of such circuits, as well as some of our recent work on techniques for mapping N-path filters to mm-wave frequencies.  Many of these techniques will then be applied to the second concept, the distributed duplexing transceiver, which combines N-path techniques with a transmitter topology akin to a distributed amplifier to allow frequency flexible FDD without off-chip diplexers.  Finally, I will briefly describe other quasi-distributed topologies for receivers that provide an additional degree of tolerance to interference when interacting with phase noise and other LO imperfections.

Light can be employed in integrated circuits in a variety of ways to enable surprising new capabilities that go well beyond traditional CMOS systems-on-chip.  Here I will discuss three non-standard ways that light can be used with CMOS circuits to enable biological sensing.  The first is a set of diffractive techniques to allow enable “angle sensitive pixels” and so enable lensed and lensless 3-D microscopy, as well as a variety of other interesting imaging capabilities.  The second is an alternate way to use angle sensitive sensors to directly digitize angle of incidence. When combined with integrated solar cells and simple signal processing and data-logging, this enables mm-scale autonomous flight-heading trackers to reconstruct flight paths of bees.  Finally, integrating micro-LEDs and photovoltaics on 100um-scale autonomous sensors allows wireless power and data transfer through tissue.   This capability enables truly dust-scale sensors for detecting electrophysiological signals, and potentially many other biologically relevant signals.  Taken together these results illuminate a variety of ways that codesign of optical and electronic functions in standard CMOS can open up valuable new capabilities for integrated circuits. 

In this presentation I will discuss N-phase passive mixers (and their close relative the “N-path filter”) as applied to interference tolerant radio receivers.  Although known for decades, the advent of deep-submicron CMOS has enabled N-path passive mixers and filters to be scaled to GHz frequencies with surprisingly good performance in both noise and linearity. I will briefly review the basic operation and properties of such circuits, and provide an intuitive analysis of the circuit and transistor properties that limit their performance, including insights into their response to phase noise.  Such N-path mixers, as originally conceived, and as implemented in the sub-10GHz regime, however, place requirements on their Local Oscillator waveforms that are ill-suited to the higher frequency (e.g. mm-wave) operation required for newer standards such as 5G. I will therefore also introduce a second set of design techniques and analytical results enable similar function at much higher frequencies

Fine grained spatiotemporal power management in digital processors and SoCs require embedded voltage regulators that are compact, energy-efficient, and able to operate over a large dynamic range. Linear regulators, including low dropout (LDO) regulators are the popular choice for on-die voltage regulation. Although analog LDOs have been used in supply sensitive load circuits over the years, there has been a recent resurgence in research and development of digitally assisted and all-digital LDOs targeted for digital load circuits. In some of these topologies, traditional design metrics such as power supply rejection, line and load regulation are often traded-off for higher energy efficiency, high performance under large current and voltage transients, as well as wide dynamic range of operation. In particular, the ability of digital topologies to regulate with ultra-low dropout voltages and down to the near threshold voltage (NTV) region have garnered significant interest. In this talk I will discuss recent advances in both circuit topologies and the corresponding control theoretical models of such LDOs. Emerging circuit topologies representing both all-digital and digitally assisted analog LDOs will be discussed. In the last part of the talk we will explore circuit topologies that unify voltage regulation and clocking circuits to provide and allow designers to reduce voltage guard-bands in digital circuits.

As we march towards the age of “ubiquitous intelligence”, we note that AI and Machine learning are progressively moving from the Cloud to the Edge devices. The success of Edge-AI is pivoted on innovative circuits and hardware that can enable inference and limited learning, in hardware-constrained ultra-low-power (uW to mW) systems – an area of active research. In this talk, I will discuss the promises and outlook of Edge-AI and their applications in Autonomous Systems; and elaborate on some of our recent work on enabling such systems in sensor nodes and robotics. While some of these systems extend our understanding of statistical machine learning, a large class of circuits and systems are inspired by the information representation in the brain. I will talk about the design of such circuits and systems with an emphasis on the impact of mixed-signal circuits, near-memory and in-memory compute architectures, non-CMOS (RRAM-based) compute macros, as well as algorithm-hardware co-design to realize the most energy-efficient Edge-AI ASICs for the next generation of smart and autonomous systems.

Several efforts of the last decade have demonstrated a radio transceiver’s ability to simultaneously transmit and receive using the same frequency band – this is commonly referred to as in-band full duplex communication. Numerous performance challenges are presented to the analog, mixed-signal and digital IC designer when attempting to suppress the strong transmitter self-interference (SI) which degrades the receiver’s SNDR. Specifically, any SI mitigation circuitry will degrade the RX’s linearity, noise figure, and reciprocal mixing performance, moreover these circuits demand high cancellation bandwidth and depth, in addition to algorithms to adapt and optimize suppression circuits in real-time. Even though integrated full duplex transceivers have been the subject of intense research, the topic of self-interference cancellation is by no means limited to wireless communication systems. In fact, many other commercial and biomedical applications benefit from the ability to suppress transmitted/emitted signals in a system that is attempting simultaneously receive, sense or record another signal. Examples include neural interfaces, radar, wireline communication and medical imaging. This presentation will begin by exploring the similarity and differences between the problem of self-interference/signal cancellation in a very diverse application space. Then, two examples of integrated self-interference cancellation systems will be presented, a neural  stimulator/sense front-end and several wireless transceivers which represent the state-of-the-art with respect to linearity, noise and cancellation depth, in addition to the ability to adapt mitigation circuitry in real-time. 

Since late 2000’s, SAR ADCs have become one of the most popular ADC architectures showing not only excellent power efficiency but also competitive conversion speed owing to the digital-friendly compact structure and architectural evolution in deep submicron technologies. Being utilized as sub building blocks, SAR ADCs could also enhance the performance of other types of ADCs such as pipelined, delta-sigma, and even flash ADCs. This talk discusses how SAR ADCs could have improved the ADC performance with various ADC architectural modification.

While SAR ADCs have become one of the most popular ADC architectures during the past decade owing to its compactness and power-efficiency in advanced CMOS processes, their limited conversion rate still remains as a major design bottleneck even with time interleaving (TI), especially in implementing high-resolution. Meanwhile, pipelined ADCs have been evolved to circumvent the opamp-based power-hungry residue generation. Often with SAR ADCs as sub-stages, recently, pipelined ADCs could achieve both high conversion rate and power efficiency. As pipelining also alleviates the calibration burden of channel-mismatch in TI ADCs owing to the reduced number of high-speed channels, this architecture needs to be improved continuously. Based on this perspective, this talk aims to provide knowledge on pipelined ADCs and recent remarkable design examples.

For over half a century, ICs have been designed and productized to advance computing performance and efficiency. Perform careful, detailed, and creative circuit design to build computing systems. With the impressive strides enabled by computing, can we now integrate computing to enhance circuit and system capabilities? If so, under which conditions and to what extent? Are there pitfalls? In this talk, we present an overview of ways and degrees in which computing can augment circuit implementations across diverse applications. These include enhancing the density and capability of neural interfaces, improving hardware security, and accelerating PLL lock time. We then examine the use of run-time computing in two applications: design of integrated voltage regulators and autonomous tracking of minimum energy point (MEP) operation. The different ways in which computing can replace or augment traditionally circuit-based solutions will be illustrated with test chip demonstrations of (1) a computationally enhanced Digital Low Dropout Regulator with 2.8-cycle mean recovery time and autonomous PVT tuning, (2) a model predictive buck regulator capable of time-optimal control under random loading conditions, and (3) autonomous MEP tracking to realize ultra-low power systems under performance guarantees. Finally, we highlight the advantages of such approaches, their current limitations, and potential for future advances.

Energy efficiency remains a key concern in modern SoCs. Despite tremendous advances in packaging and power delivery, the margins required to withstand supply voltage noise still play a dominant role in dictating SoC energy efficiency. Starting from early efforts that injected charge into the supply, the field has evolved toward instruction throttling and adaptive clocking which have become widely adopted. Even so, there remains significant room for further margin reduction. In this talk, we briefly introduce the problem of supply noise and examine several adaptive clocking techniques that have been adopted over the years to address this challenge. We examine their existing limitations to motivate the design of several recent adaptive clocking innovations that unify voltage regulation and clock generation into a single entity. In particular, the talk will focus on the Unified Clock and Power (UniCaP) architecture. The effectiveness of this technology and its enabling capabilities will be discussed through multiple test-chip demonstrations and measurements. These include a performance-regulated 65nm Cortex M0 processor which achieves 98% voltage margin reduction, a frequency-locked sub-threshold processor that demonstrates 90% margin reduction while tracking both temperature variation and voltage noise, and a more recent SIMO implementation that draws 58% lower power than a conventional iso-performance implementation. Finally, we discuss some UniCaP limitations that inform both its existing usability and future directions.

With datacenters mushrooming around each other to provide the necessary bandwidth for our computing and communication needs, the need to interconnect them with optical fibers at low cost and high energy efficiency has significantly increased. Coherent silicon photonic links bear the promise to satisfy that demand at an unprecedented scale, integration, and (low) cost. In this talk, I will briefly introduce silicon photonics, describe our recent work on silicon photonics 16-QAM coherent links operating at 0.5Tb/s, and comment on some of the subsequent research opportunities in coherent silicon photonics.

What is a good frequency synthesizer? A survey of CMOS phase-locked loops (PLLs) over the last two decades shows that the overall performance of PLL-based frequency synthesizers is bounded by a tradeoff between noise, area, and power consumption. Analog PLLs with a charge-pump integrator (Type-II) suffer from charge-pump and detector noise, and are area- and power-hungry. All-digital PLLs are compact and friendly to technology scaling but limited in noise performance under a restrained power budget. 

The simplest frequency synthesizer is one utilizing the least noise-inducing components in the loop. The recipe to design the lowest noise synthesizer is simple: (1) Choose the VCO with the lowest phase noise. (2) Reduce its low-offset phase noise by locking it to the cleanest frequency reference with a large loop bandwidth. (3) Eliminate/suppress other noise sources. Such a loop can be realized as Type-I, without an integrator in the loop filter. Such synthesizers thus comprise subsampling Type-I PLLs and injection-locked (Type-I) PLLs. They achieve low noise performance in a compact footprint and low power budget. And the limitations of classical Type-I, subsampling, and injection-locked topologies can be remedied using two classical design philosophies - 1) a simple design is often a good design, and 2) use digital CMOS where it is good at. Such digitally-assisted analog synthesizers include the best of both worlds.

In-band Simultaneous Full-Duplex (FD) radio communication, where the transmitter and the receiver operate on the same frequency band at the same time, has been explored as a means to increase the throughput in the last decade. The hurdle in achieving FD is the self-interference (SI) from the transmitter that is several orders of magnitude stronger than the desired signal at the RX. For mobile applications, SI cancellation circuits should be low-power, linear, tunable, low-noise, fully monolithic with a compact form factor, and implemented at the radio frequency front-end. I will describe the challenges in designing an FD single-chip radio for WiFi/ cellular applications, give an overview of the state-of-the-art, and present our work to achieve large delay/broadband cancellation. I will then describe the outstanding challenges toward FD deployment for WiFi/cellular applications. I will also present other wireless applications where FD promises a significant performance improvement.

The devices in the arsenal of a CMOS designer include resistors, capacitors, inductors, and transistors. What happens when we add light to that? With an ability to move the information between electrons and photons, many new opportunities and applications will emerge. In the last five years, silicon photonics - where light is guided in a silicon waveguide on a CMOS SOI process, has already had a significant impact in the field of high-speed transceivers for data communications. 

Which applications will become mainstream in the next 5-10 years? Sensing? Computing? RF & Microwave? Quantum? What will be next in communications? 

And how can we easily add photonics to the arsenal of the CMOS designer and make its adoption seamless? I will attempt to answer some of these questions in this talk. I will also highlight the opportunities that lie ahead for a CMOS designer in adopting this technology - now ready to be deployed.

The sampling kT/C noise is traditionally deemed as a fundamental SNR limit for Nyquist-rate ADCs. To suppress it, the only option is to increase C. Nevertheless, this leads to significant challenges for the ADC input driver and the reference buffer. In fact, the ADC driver and reference buffer are the system bottleneck nowadays. Their power, area, and design complexity can be an order of magnitude higher than the ADC core. Since the root cause of this challenge is the large C, it is highly desirable to break this seemingly fundamental tradeoff between the capacitor size and the kT/C noise. This talk will introduce two techniques that can significantly reduce the capacitor size but without incurring large kT/C noise penalty. The first technique is to operate a SAR ADC in the continuous time to completely avoid the need for the sampling operation. The second is to cancel the kT/C noise using a novel two-step sampling operation. Both techniques can achieve high resolution with orders of magnitude reduction in the capacitance size, thereby substantially relaxing the requirement for the ADC input driver and reference buffer.

Conventional sensor front-end designs all follow the Nyquist theorem that the data acquisition rate must be at least twice the signal bandwidth. Nevertheless, it is not an efficient way to capture a sparse signal, for its information rate can be much lower than suggested by its bandwidth. In fact, many natural signals are sparse including audio, image, and biological signals. Compressive sensing (CS) is a technique that takes advantage of the natural signal’s sparsity and allows the signal to be precisely captured with far fewer measurements than the Nyquist rate. Thus, it opens up a new door to reduce the sensor power. This talk discusses the opportunities and challenges in applying CS techniques to sensor front-end design. Focus will be given on how to develop a hardware-efficient circuit realization for CS. We will cover both single- and multi-channel CS architectures for audio and imager applications. 

This talk introduces a new type of dynamic amplifier, the floating inverter amplifier (FIA). FIA enables current reuse and dynamic biasing, thus achieving excellent energy efficiency. It provides robust operation against process, voltage, and temperature (PVT) variations. Moreover, its output common-mode voltage is well controlled without the need for an explicit common-mode feedback circuit. Two example applications will be described: 1) by performing pre-amplification for the comparator, it enables the most energy-efficient comparator reported to date; 2) two FIAs are cascaded to realize the world’s first high-performance closed-loop dynamic amplifier, which offers high resolution, high energy efficiency, and PVT robustness simultaneously. It makes possible the first fully dynamic noise-shaping SAR ADC with sharp noise transfer function and no calibration.

SAR is widely used for medium resolution applications due to its simplicity, scaling compatibility, and low-power consumption. However, its power efficiency degrades as the resolution increases due to its tight requirement on the comparator noise and the exponentially growing capacitor DAC array. By contrast, DS ADC is a popular architecture for high-resolution applications. Taking advantage of noise shaping, it can achieve high resolution with a low-resolution quantizer and DAC. However, it typically requires the use of op-amps that are power hungry and scaling unfriendly. This talk will present latest hybrid ADCs that aim to combine the merits of SAR and DS while simultaneously obviating their drawbacks. After providing a high-level review of published works, this talk will take a deep dive into two interesting noise-shaping SAR ADC architectures. The first one uses fully passive switched-capacitor filter to achieve 2nd-order noise shaping. It is fully dynamic and can be easily duty cycled. In addition, it is robust and calibration free. Thus, it is well suited for low-power sensor applications. The second one adopts an error-feedback structure, which simplifies the filter design. It consumes very low power by using a dynamic amplifier and address its process, voltage, and temperature (PVT) sensitivity via a fast-convergence background calibration loop. 

“Interconnect Gap” has been a long-standing grand challenge caused by the gap between the ever-increasing data rate demand and the insufficient capabilities. The capacity challenge is further deteriorated with simultaneous challenges of energy efficiency and cost. Existing electrical interconnect (EI) and optical interconnect (OI) face fundamental difficulties to completely address the interconnect issues individually. THz Interconnect (TI), utilizing the frequency spectrum sandwiched between microwave and optical frequencies, holds the high potentials to complement EI and OI by leveraging the advantages of both electronics and optics. In this talk, I will present our research activities in the high potential TI field, including THz silicon waveguide channel development, TI system demonstration, dispersion constrained link bandwidth and mitigation schemes such as mode division and frequency division multiplexing based channelization.

3D stacking and backside illuminated (BSI) CMOS image sensor (CIS) manufacturing technologies offer a means to unleash the full potential of single photon avalanche diode (SPAD) sensors. Optimised BSI SPADs with small pitch, high detection efficiency, low noise and broad spectral range have recently been developed. Digital processing placed under these SPADs has leaped to advanced digital 40/22nm nodes matching those adopted in state-of-the-art stacked-BSI CIS. Unlike CIS, SPAD pixels require no analogue processing and offer relatively large areas for embedded digital signal processing. This offers new potential for image sensor designers to implement direct Time of Flight (dToF) imaging and time-correlated single photon counting (TCSPC) on a massively parallel scale.  Power efficiency and timing uniformity represent a particular challenge of these devices given the high charge per pulse of detectors and large simultaneous power draw of time to digital converters operating at GHz frequencies. Huge data volumes generated by SPADs firing collectively at Giga-events/s in high ambient scenarios must be handled by novel sharing and time multiplexing of digital pixel processing resources. This talk will review some of these recent advances in stacked 3D SPAD pixel and sensor architectures including examples drawn from the author’s own work. Technology trends and future pixel scaling possibilities will be discussed.

Advanced manufacturing technologies originally developed for CMOS image sensors have catapulted single photon avalanche diode arrays into the mainstream of imaging leading to volume products in the 3D time of flight imaging and automotive LIDAR. Medical and scientific applications have been slower to emerge but are poised to leverage the wide spectral range, high detection efficiency, low dark noise, picosecond resolution and dense digital integration provided by these technology platforms. This talk will highlight CMOS SPAD solutions to a number of medical and scientific applications including Positron Emission Tomography (PET), fluorescence lifetime imaging for microscopy and cancer margin endoscopy, optical neural interfaces and Raman spectroscopy. The circuit architectures will be reviewed illustrating the symbiosis with 3D time of flight technology. The prospects for future advances exploiting recent 3D stacked process trends will be examined.

Single photon detectors such as single photon avalanche diodes (SPADs) have been traditionally deployed for low light sensing in scientific, radiation or microscopy applications. In the last few years, there has been a huge upsurge of interest in the use of SPAD detectors for low cost, mass market LIDAR for artificial reality (AR/VR) or automated driving assistance (ADAS). In these applications the detectors must tolerate high levels of solar background flux requiring a high dynamic range in the time domain rather than the charge or voltage domain. This requires the entire signal chain of the SPAD direct Time of Flight (dToF) sensors to be reconsidered from a legacy of scientific TCSPC electronics exploiting the sparsity of photon arrivals in low light conditions. A variety of solutions such as pixel combining techniques, partial histogramming and multi-event TDC architectures have been proposed. We will compare these approaches with respect to background conditions, laser power, angular and depth resolution and present the SPAD receiver challenges for both flash and scanning lidar systems.

This tutorial will highlight advanced modeling and simulation methods to estimate various performance metrics such as bit-error rate (BER), eye-opening, and jitter tolerance (JTOL) of state-of-the-art high-speed I/O interfaces. Specifically, the talk will address how to model interferences and noises present in I/O systems and estimate BERs using efficient statistical simulation techniques. Topics of interest include: modeling the nonlinear distortion, finite aperture, and noise in analog front-end circuits such as equalizers and clocked comparators; assessing the effects of power-supply noise and feedback latency in digitally-controlled timing circuits such as PLLs and CDRs; simulating the transient and steady-state behaviors of various calibration loops such as equalizer adaptation loops and offset calibration loops; and evaluating design trade-offs in ADC-based links.

Today’s SoC designs are neither purely digital nor purely analog; they are mixtures of both. As SPICE simulators face difficulty in handling such large circuits at the system level, modeling the analog circuits in SystemVerilog and verifying the whole system using digital verification flows such as UVM is becoming a common practice. This talk addresses ways to auto-extract models from analog circuits and run efficient simulations with them in an event-driven logic simulator like SystemVerilog.
It all starts with how we express analog waveforms. Using equations instead of points, the event-driven algorithm of SystemVerilog can be extended to analog simulations, even to transistor-level circuits exchanging voltages and currents. This also opens the door to automated ways of extracting models from circuits. Using a set of model templates both at the device level and at the circuit level, the models with SPICE-accurate characteristics can be auto-generated from the circuits. These analog models running in SystemVerilog can deliver up to ~100x speed-up’s compared to running SPICE.

The recent development in neural networks has required massive data transfer between memory and processing elements for data processing. This heavy data transfer leads to substantial energy overhead and limits the overall performance of the neural networks. Computing-in-memory (CIM) has attracted the research community’s attention because of the significant energy efficiency improvement by minimizing the energy-hungry data transfer. CIM designs can employ either analog computing or digital computing, while each has its pros and cons. In this talk, I will present the basics of CIM design and various challenges. After that, various state-of-the-art CIM macros will be introduced. I will also discuss analog and digital CIM macros and their applications. In the last part, I will present CIM designs based on emerging non-volatile memory devices and their applications.

Various battery-powered ultra-low power applications such as Internet-of-Things (IoT), wearable devices, biomedical devices, and tiny machine learning have opened up a new domain of integrated circuits design. In these applications, minimizing energy is the most critical research focus. Since embedded memories, dominated by SRAMs, occupy substantial power and energy in the IoT devices, designing energy-efficient embedded memories is a critical task for enhancing the lifetime of IoT devices. In this talk, I will present the basics in ultra-low power SRAMs followed by state-of-the-art ultra-low power SRAM design techniques. Several emerging applications of SRAM will also be introduced. Finally, I will discuss future directions in ultra-low power embedded memory for IoT applications.

Recent developments in artificial intelligence (AI) and machine learning (ML) have created a growing interest in neural networks for smart IoT devices. However, it is critical to design energy-constrained neural networks because of the limited energy supply. Many well-known neural network models are not suitable for IoT applications whose energy is from a battery or an energy harvesting device with a limited form factor. In this talk, I will present various design considerations for ultra-low power application-specific tiny ML accelerators for smart IoT devices, followed by introducing several energy-efficient tiny ML accelerators and computing-in-memory macros for smart IoT applications.

LC VCOs are commonly used for RF carrier generation. A wide tuning range in a single VCO is desirable for covering multiple bands while occupying a small area. An octave tuning range enables continuous coverage of all lower frequencies by integer frequency division. LC VCOs are most often tuned using variable capacitor banks and varactors. Because of switch resistances in capacitor banks and poor quality factor of varactors, using only capacitors for tuning degrades the phase noise, especially at millimeter-wave frequencies. Variable inductors using series switches pose the same problem. Mutual coupling can be exploited to realize multiple resonant modes with different effective inductances without using switches. This allows a wider tuning range without substantial reduction in the tank quality factor. Topologies for multi-mode resonant structures and their performance will be described with examples from the literature.

Gate driver circuits to ensure proper turn-on and turn-off for power switches are essential parts of a power converter design. They become significantly challenging for multilevel converters where multiple switches are operated at active voltage domains. Recent favorable use of Gallium-Nitride (GaN) devices for power switches makes gate driving even more difficult as the switch performance and reliability are very sensitive to variations of the gate driving signals and power rails compared with traditional power MOSFETs. In this talk, the speaker will discuss different gate driving methods with a multi-level multi-inductor hybrid (MIH) converter as the demonstration prototype to address two key challenges in designing gate drivers: 1) providing level-shifted PWM signals to active voltage domains and 2) powering schemes for gate driver circuits. The design techniques of gate drivers in both discrete implementation and integrated circuits will be covered to provide the perspective and design guidelines in high-voltage integrated power converter design.

While integrated power converter is required in every modern electronic system, designing one that achieves both area- and power-efficient continues to be a big challenge in many engineering teams. In this talk, the speaker will discuss a good design flow and a number of useful techniques in designing integrated power converters that he has accumulated over the last ~20 years of his career. The flow includes a process of coming up with a converter concept; discussing topology trade-off; a general, fundamental, but intuitive loss analysis and optimization; and desgin verification. Design techniques include different circuit techniques and important layout considerations.

The need for an efficient power management solution has never been more critical across virtually all electronic devices and systems from low power to high power, smartphones to data centers, battery-powered components to renewable-energy-powered grids, and from stationary systems to aircraft. The key, common challenge for power management in these systems is to satisfy increasingly demanding requirements in terms of efficiency, size, reliability, and cost, simultaneously. This talk will present a unique flow of integrated power converter architectures, topologies, and circuit techniques to address this challenge. Particularly, the speaker will discuss his group research work on a family of hybrid converters that achieve high efficiency for high output power density and current density.

Due to the integration of everyday objects to the open network, securing private data and preventing its leakage has become one of the most important concerns in the Internet-of-Things era. Physically unclonable functions (PUFs) have drawn attention as one of the key security primitives for IoT devices since they can provide unique, random, stable, and unclonable hardware fingerprints for secure communications. In this talk, key design challenges and recent design trend of PUF are presented in two aspects: 1) random key generation with entropy sources and 2) stabilization of the generated keys. Then, recent examples of cost-effective PUF implementations enable by compact entropy source implementation and lossless stabilization schemes are introduced.

Near-threshold voltage (NTV) computing offers a promising approach to achieve high energy efficiency, but its voltage scaling is limited by its sensitivity to PVT variations. To achieve energy-efficient and robust operation at NTV, the following attributes are required for sequential circuits: 1) fully static operation, 2) contention-free transitions, 3) no redundant internal toggling to minimize power consumption and 4) minimum area overhead. To date, reported flip-flop designs with single phase clock experience residual internal clock toggling, and/or functional failure due to lack of attributes 1 or 2. In this talk, the key attributes for low power flip-flops are reviewed and recent flip-flop designs that satisfies all aforementioned attributes, which makes it capable of low power and low voltage operations at NTV, are introduced.

Bi-directional Device-to-device (D2D) wireless power transfer, a.k.a. reverse wireless charging or wireless PowerShare, has been a fancy selling point for the flagship smartphone models. Yet, the power level and efficiency of the current solutions are relative low, or the size and cost are constrained. The magnetic coupling coils, where are made by long wires, unavoidably have relatively large parasitic resistances. To increase the wireless charging power and efficiency, high AC voltages on the coupling coils are favorable for reducing their conduction losses. Prior arts design the DC-DC conversion and DC-AC inversion or AC-DC rectification separately. In this talk, we will present our hybrid power conversion topologies that combine and merge the DC-DC and DC-AC/AC-DC stages, for the next-generation D2D wireless fast charging. 

With the rapid growing demands on data transmission and processing in a world of big data and artificial intelligence, the power consumption of the information industry sees an exponential increase. Then, the energy efficiency of the microprocessors becomes more and more important, from both thermal and energy perspectives. Per-core dynamic voltage and frequency scaling (DVFS) technology is proven to be an effective way to improve the digital system energy efficiency. But, per-core DVFS requires high current density fast-transient integrated voltage regulators (IVRs) at the point-of-load (PoL) to enable and support it. Recently, the advanced 3D packaging technologies enable more design flexibility and topology innovations for the PoL IVRs. This talk will introduce our recent advances on PoL IVRs, including switching power converters as well as linear low-dropout regulators.

TIAs are employed in many different systems, from wireless transceivers to qubit manipulation and readout in quantum computing or as low-noise amplifiers in optical receivers front-ends.

In this talk a few TIA design examples will be presented, covering different type of applications.

Performance requirements change dramatically depending on the application, leading to a wide variety of implementation styles and circuit techniques.

TIAs can be broadly grouped into two categories, i.e. closed-loop and open-loop topologies. 

Closed loop TIAs generally have better frequency response precision and can achieve higher dynamic range, but typically have higher power dissipation and limited bandwidth.

Open loop topologies are preferred when very wide bandwidth or ultra-low power dissipations are required.

Nearly every wireless receiver includes a TIA after the down-conversion mixer.

In wireless sensor networks or Internet-of-Things (IoT), bandwidth is limited but power dissipation is reduced to a minimum, leading to ultra-low-power TIAs that consume only a few uW.

In 5G FR1 receivers, TIAs with tens of MHz bandwidth and very high dynamic range are required. Closed-loop architectures are dominant, often with complex op-amp architecture and with and power consumptions in the order of a few mW.

In 5G FR2 receivers, TIAs with hundreds of MHz to a few GHz bandwidth are used, mostly based on open-loop topologies with power dissipations of tens of mW.

To conclude the overview, TIAs for electro-optical interfaces will be presented. In optical receivers a low-noise TIA is required to amplify the current detected by the photodiode. These TIAs have tens of GHz of bandwidth and can consume up to hundreds of mW power.

Biological processes such as neuronal signaling and cell growth are among the most complex micro- and nano-scale processes in nature. Historically such processes have been studied at system level because there were no tools available to study individual components of the process. However, cellular-level interfacing is needed to provide better understanding of the brain and to develop more advanced prosthetic devices and brain-machine interfaces. With semiconductor technology innovations, much recent work has been focused on unraveling biological complexity, but also on driving new diagnoses, treatments and therapies that are tailored to the individual. One of the drivers behind those innovations is novel CMOS circuits enabling multi-modal, high-precision data collection and analysis at ultra-low power consumption. In this talk, I will present recent biomedical developments based on silicon technology, and I will discuss the requirements, materials, circuit techniques and design challenges of their ASIC and SoC platforms.

The ability to detect single photons with high sensitivity and precision is revolutionizing the image sensors field. Single-photon avalanche diodes (SPAD) not only are extremely sensitive, but they also retain with high accuracy the photon arrival time, which opens a whole new world of opportunities. Conventional image sensors circuitry is not anymore enough to manage this device, which requires a completely different readout chain.

In this lecture an overview of the SPAD potential, with pros and cons, will be addressed. Typical circuit topologies employed in SPAD-based image sensors will be described, along with some examples of applications and current trends.

3D imaging arrived to the mainstream products and gadgets very recently, but it is under development since more than 20 years. Now, it serves applications ranging from consumer to automotive, from industrial production to space exploration. There are several solid-state techniques enabling 3D sensing and imaging, among which time-of-flight (ToF) is one of the most prominent.

In this lecture, the different techniques, devices, and circuits needed to address the realization of a solid-state ToF sensor or imager will be discussed, highlighting the specific challenges, the different application requirements and existing architectures.

We are used to capture images with our eyes – and cameras – using only visible light: however, different wavelengths carry different kind of information. There’s an interesting part of the electromagnetic spectrum called the Terahertz region (approximately from 100GHz to 10THz) where, at the borders of photonics and electronics, it is possible to realize imaging with particular features. Indeed, the transparency of dielectrics, the presence of spectral fingerprints of materials, and the non-ionizing nature of the radiation gathered a lot of attention.

In this lecture the methods to perform sensing and imaging with THz radiation, in particular exploiting simple FETs in standard CMOS technology, will be analyzed. As the signal to be detected is very weak, it poses the challenge of ultralow noise readout: therefore, a number of circuit alternatives will be shown.

On-chip communication directly impacts the performance, energy efficiency, and area of systems-on-chip, multi-processors and highly-parallel accelerators, especially for emerging machine learning applications. In this talk, I will introduce a range of design options for on-chip interconnects, from point-to-point links to complex network topologies, starting from architecture to low-level circuit techniques. The presentation addresses base routing schemes and mapping of different protocol families, such as data-flow or address-map based communication, up to memory coherence traffic. Moving on to microarchitecture, it presents flow-control and arbitration requirements and options. I will then detail circuit-level considerations, with a focus on different synchronization strategies across multiple clock domains, including multi-synchronous, source-synchronous-clocking, and fully-asynchronous circuits, to finally introduce the potential of 3D-chip integration for on-chip communication.

Deep neural networks (DNNs) have emerged as a key approach to solving complex problems across many application spaces, including image recognition, natural language processing, robotics, health care, and autonomous driving. Designing custom hardware accelerators for deep neural networks is highly promising, as they offer significant performance and power advantages compared to general-purpose processors.  This talk presents a hardware-software co-design framework called MAGNet that takes an application specification as input and produces an ASIC accelerator along with valid mappings for running the target networks. It explores different data formats, quantization techniques, memory hierarchies, and dataflow. A new data format called VS-Quant, which employs a per-vector scaled quantization scheme that employs a two-level scaling scheme for achieving low-precision computation is discussed. It presents novel multi-level dataflows that achieve reuse across different operands to improve energy efficiency.

Deep Neural Network (DNN) use cases range have diverse performance and power targets. These are highly compute-intensive and have growing demands as DNN models get larger and more complex. Package-level integration using multi-chip-modules (MCMs) is a promising approach for building large-scale systems. While accelerators fabricated on a single monolithic chip are optimal for specific network sizes, MCM-based architecture enables flexible scaling for efficient inference on a wide range of DNNs, from mobile to data center domains. This talk explores the benefits of using MCMs with fine-grained chiplets for scaling DNN inference. It presents a 36-chiplet prototype MCM system for deep-learning. The MCM is configurable to support a flexible mapping of DNN layers to the distributed compute and storage units. Communication energy is minimized with large on-chip distributed weight storage and a hierarchical network-on-chip and network-on-package, and inference energy is minimized through extensive data reuse.

Cell-based, synthesizable mixed-signal circuits such as ADPLLs, ADCs, and LDO are gaining significant traction. This is fueled by the exponentially increasing number of DRC rules in advanced nodes, added restrictions on custom layout, and overall increase in design time for full-custom, analog designs. This talk focuses on different techniques for cell-based analog designs that are amenable to using existing automatic place and route tools to automate their physical design, thereby significantly reducing design time.

Efficient and robust wireless connectivity is a requirement for most IoT applications. The radios need to be low power while still providing sufficient range and co-existing with other radios that share the same frequency bands. Supporting wireless standards is key for adoption and ubiquitous integration with the existing wireless infrastructure, but is often at odds with ultra-low power radio design. This presentation will start with a review of ultra-low power receivers reported in literature, followed by an overview of recent design trends and a discussion of what the future holds for ultra-low power radios for IoT applications.

5G is the latest global wireless standard, which increases peak data rates and connection densities tenfold compared to 4G LTE. To achieve such a superior wireless link, 3GPP 5G standards utilize both sub-6-GHz and millimeter-wave (mm-wave) frequency bands with wider aggregated channel bandwidth; multiple-input, multiple-output (MIMO) techniques; and complex modulations. These approaches all demand stringent phase noise and spurious tone performance of the local oscillator (LO). This talk provides an overview of the major LO design considerations and low-jitter frequency synthesis techniques for 5G New Radio, focusing on millimeter wave frequency bands for handset applications. It starts with frequency generation requirements and LO topology comparison, and then focuses on phase-locked loop (PLL) architecture design. Finally, circuit design techniques for key building blocks will be elaborated, including phase detectors (PDs), oscillators, and frequency multipliers.

High performance fractional-N phase-locked loops (PLLs) are essential elements of any advanced electronic systems. In recent years, both analog and all-digital PLLs employing sampling or sub-sampling phase detector have gained popularity and demonstrated below 100-fs integrated jitter and superior figure-of-merit. This talk focuses on this PLL architecture and elaborates the advanced design techniques to achieve low jitter, low fractional spurs, fast locking, and low power operation. Both circuits design and digital calibration techniques will be presented in detail. In addition, recent advances in reference clock generation will also be discussed as it is crucial for high performance PLLs.