Wide power-performance adaptation is becoming crucial in always-on nearly real-time and energy-autonomous integrated systems that are subject to wide variability in the power availability and the performance target. Adaptation is indeed a prerequisite to assure continuous operation in spite of the widely fluctuating energy/power source (e.g., energy harvester), and to grant swift response upon the occurrence of events of interest (e.g., on-chip data analytics), while maintaining extremely low consumption in the common case. These requirements have led to the strong demand of a new breed of integrated systems having an extremely wide performance-power scalability and adaptation, beyond conventional voltage scaling or adaptive parallelism. In this talk, new techniques that drastically extend the performance-power scalability of digital circuits and architectures are presented. Silicon demonstrations of better-than-voltage-scaling adaptation to the workload are illustrated for both the data path (i.e., microarchitecture) and the clock path. Adaptation to a very wide range of energy/power availability is also discussed, presenting demonstrations of always-on systems (e.g., microcontrollers, power management units) with power down to sub-nW, and duty-cycled operation down to pW range. Several silicon demonstrations are illustrated to quantify the benefits offered by wide power-performance adaptation, and identify opportunities and challenges for the decade ahead.

The historical 100X/decade energy down-scaling is currently being threatened by the end of Moore’s law, and the limited prospective energy gains from approaches that have been already exploited extensively (e.g., heterogeneous systems, ultra-low voltage, parallelism). Major shifts from traditional sensing/processing paradigms are now mandatory, and new design dimensions that enable further energy reductions need to be explored, to sustain continuous miniaturization, lifetime and cost improvements.
In this talk, energy-quality (EQ) scalable circuits and systems are introduced as a fundamental direction to continue the historical exponential energy down-scaling. The CAS community is currently focusing on this new field, which is also the theme of major journal special issues. EQ-scalable systems dynamically and explicitly trade off energy and quality from sensor to circuit, architecture, algorithm, and up to system level. Recent and novel approaches are discussed to minimize the energy at run time, based on the actual quality target that is set by the specific task, the context, and the specific dataset at hand. Quality is treated as an explicit knob, eliminating the quality slack that is traditionally imposed by worst-case design across different applications, contexts, datasets, and the pessimistic design margin to counteract process/voltage/temperature variations. Interesting convergence with machine learning and other important applications is discussed to provide an insight into the inter-dependence of algorithms, architectures and circuits. Several silicon demonstrations are illustrated to quantify the benefits offered by energy-quality scaling, and to describe the challenges that need to be solved to fulfill its potential.

Batteries pose fundamental threats to the further advancement of systems for ubiquitous sensing and intelligence (e.g., Internet of Things, devices for healthcare, smart objects/systems). Batteries are indeed a major cost and form factor bottleneck in single-chip integrated systems, and will also have a very heavy environmental impact when deployed (and disposed) at the expected scale of one trillion connected devices.
In this talk, state-of-the-art techniques for battery-lightweight and battery-less integrated systems with always-on operation are introduced. From a top-down viewpoint, system architectures are introduced to enable continuous adaptation to workload and harvested power/battery energy availability. Time- and event-driven frameworks are introduced and exemplified with several silicon demonstrations, along with duty-cycled and always-on schemes. From a bottom-up perspective, advanced circuit techniques are introduced to enable uninterrupted operation under uncommonly wide range of available harvested power, and/or very limited battery energy. The talk covers all major sub-systems along the on-chip signal chain, from energy harvesting to power delivery, analog interfaces, digital processing, and higher-level signal sensemaking. Edge computing, machine intelligence and in-memory computing are discussed as crucial enablers of continuous event monitoring and efficient energy usage at the system level. The related concepts are exemplified by integrated prototypes from industry and academia.

Security is finally being generally perceived (and often required) as an important attribute of hardware systems, as a result of several breaches and vulnerabilities that have been brought to the attention of the general public. Hardware security is now progressively becoming closer to ubiquitous in space and always-on in time, as the related building blocks and sub-systems need to be an essential part of any integrated system down to tightly power-constrained systems (e.g., nodes for the Internet of Things).
In this talk, pervasive hardware security is discussed in a broad sense, encompassing methods that assure security in every System on Chip (SoC), as well as in critical SoC components. From an SoC viewpoint, recent trends in energy efficiency are analyzed and put in perspective to identify the opportunities to embed security solutions down to low-end SoCs and in an always-on fashion. From an SoC component viewpoint, immersed-in-logic security primitives are discussed to highlight how security can be pervasive within each component, while keeping the system integration effort to a minimum. Cost-aware design methods are also discussed, being cost a major factor that decides whether a security feature is incorporated in real-world systems or not. Several silicon demonstrations are illustrated to quantify the benefits and the limits of existing techniques, and identify opportunities and challenges for the decade ahead. At the end of the talk, fundamental directions on how to make hardware security more pervasive and unceasing are discussed.

Over the last few years, a significant growth of the research involving the use of microwaves to image the human body has been taking place. Among the many examples of ongoing research, the use of microwaves for breast cancer diagnostic imaging has seen an increasing interest. Ultra wideband microwave radar imaging can effectively complement conventional diagnostic techniques, e.g. X‐ray, MRI, ultrasound, yielding higher sensibility and specificity, lower cost, and smaller size, hence emerging as an enabling technology for mass screening programs. Ultra wideband radars can be realized in different technologies, discrete or fully integrated. This talk investigates the typical system and circuit-level challenges of such radars, and discusses some implementation examples. The talk presents innovative circuit solutions addressing the challenges set by the ultra wideband frequency range of operation of the radar transceiver. Due to their broadband operation, such design techniques may find application in other wideband systems.

Integrated magnetic transformers are becoming ubiquitous in mm-wave and RF systems, while also finding application in fully-integrated dcdc converters. This talk will cover the fundamentals of the transformer operation spanning from the underlying physical principles, to the link between the magnetic parameters (inductances and magnetic coupling) and the geometry of the device, to its use in the design of building blocks like LNA’s, PA’s, VCO’s, etc. The advantages and possibilities of using a transformer for the implementation of baluns, impedance transformation networks, higher-order resonant networks, feedback circuits, etc., will be highlighted.

The talk will deal with the design of low-phase noise voltage-controlled harmonic oscillators (VCOs) implemented in bipolar technologies. The design challenges related to achieving minimum phase noise for a given set of technology parameters (supply voltage, metal stack, varactor devices, etc.) will be discussed with particular emphasis to attaining low phase noise while using varactor diodes, to the use of magnetic transformers in the resonator, and to the selection of the most appropriate oscillator topology. Effective techniques to tackle such issues will be illustrated. Design examples of VCOs operating in the K-band and suitable for 5G applications will be presented.

Cellular technology has witnessed five generations of evolution - the mobile UE-era ushered in by 2G (GSM/EDGE), to the future smart-phones that will powered by the enhanced spectral efficiency of 5G. Each 'G' improved the user experience while introducing new hardware design challenges. I compare 2/3/4/5G system requirements, derive key TX/RX/LO circuit specifications, and highlight the differences in circuit topologies suited for these contrasting specifications. Using this framework, circuit techniques to handle a diverse range of problems such as low phase-noise oscillators, improved blocker tolerance, single-RB linearity will be introduced.

The explosive growth services delivered via the internet onto the mobile handset has result in an insatiable demand for higher data-rates. Millimeter-wave CMOS radios – a research topic for over a decade – is now finally on the cusp of large-scale deployment. In this talk I will describe the challenges and state-of-the-art in circuits and architectures for 28GHz/38GHz 5G NR transceivers targeting user-equipment or UE applications.

Modern SoCs for advanced applications are integrating an increasing number of phase-locked loops (PLLs) into a single silicon die. 5G transceivers require multiple PLLs to implement complex schemes of carrier aggregation and MIMO. Multi-core processors also have to use many PLLs to generate independent clock frequencies for each core to operate at the optimum performance. With this trend, an area-efficient design of PLLs becomes more important. In this point of view, i.e., the efficiency in the use of silicon, ring-oscillator-based digital PLLs (DPLLs) have obvious merits over conventional LC VCO-based charge-pump PLLs. Ring-oscillator-based DPLLs also have an advantage in terms of the scalability with new CMOS technologies. They also can be implemented in some CMOS technologies where high-quality metal layers for inductors are not available. Despite foregoing merits, their poor jitter performance has limited their popularity in high-performance applications that generally require a clock signal having an ultra-low jitter. This lecture introduces recent architectures of low-jitter ring-oscillator-based DPLLs and presents key enabling circuit techniques to resolve their problems, such as thermal and flicker noises of ring oscillators, reference spurs, and fractional spurs. Finally, we discuss the limit of ring-oscillator-based DPLLs and the possibility of their adaptation to high-performance applications.

As the data rates of both wireless and wireline communication systems increase, the generation of millimeter-wave-band (mmW-band) signals that have ultra-low phase noise becomes more important for the design of the transceivers. The standard of the fifth-generation (5G) mobile system defines new radio frequencies in mmW bands from 24 to 40 GHz. To support high-order modulations, such as 256 QAM, the value of the EVM must be reduced to less than –30 dB, implying that mmW-band local-oscillating signals must have an extremely low IPN, e.g., less than −36 dBc. Similarly, to satisfy the Nyquist criterion and minimize the effect of channel mixing, direct RF-data converters using high-speed analog-to-digital converters (ADCs) also require mmW-band clock signals that have very low RMS jitter. The demands on the performance of the ultra-low jitter for mmW-band signals also have increased recently in advanced, high-speed serial links, in which the target data rates have increased to more than 100 Gb/s. As shown above, mmW-band signals are used in many different advanced applications, but they commonly are expected to have sub-100 fs RMS jitter values. This lecture introduces recent architectures of frequency synthesizers that can generate ultra-low-jitter mmW-band signals, based on a cascaded architecture consisting of a ultra-low-jitter GHz-range PLL and a wideband mmW-band injection-locked frequency multiplier.

Continuous increases in the data rates of communication systems demand further improvement in the jitter performance of clock signals. To date, conventional phase-locked loops (PLLs) using an LC-type voltage-controlled oscillator (LC-VCO) have been used the most widely in practical applications. However, the critical problem of LC-VCO-based PLLs is a large silicon area. Ring VCO-based injection-locked clock multipliers (ILCMs) are considered as an alternative solution. In ILCMs, the phase of the output edges of a free-running VCO is corrected naturally by periodically injected reference signals. This phase-realignment mechanism of an ILCM is capable of creating a much higher cutoff frequency of the noise transfer function (NTF) of the VCO compared to conventional PLLs, thereby resulting in the much greater suppression of the jitter of ring VCOs. Despite the superiority of ILCMs in the reduction of the jitter of ring VCOs, ILCMs have a critical problem in that the performances of RMS jitter and reference spur are degraded significantly due to PVT variations. This problem asks for intensive background calibration techniques that can remove any phase errors of ILCMs in a real-time fashion. This lecture presents ring-VCO-based ILCMs that can achieve a low reference spur as well as a low RMS jitter and the design of versatile background calibration techniques that can help ILCMs maintain good jitter performance.

Piezoelectric energy harvester (PEH) is one of the most promising candidate for ambient vibration energy scavenging for ubiquitous miniaturized Internet of Things (IoT) devices. Due to the PEH inherent capacitance, the extractable AC-DC electrical power in traditional PEH interface using full-bridge rectifier (FBR) is limited. Existing PEH interfaces generally employ non-linear techniques such as the parallel-synchronized-switch harvesting-on-inductor (P-SSHI) and fractional open circuit technique to enhance the extracted power and achieve efficient maximum power point tracking (MPPT). However, they typically require bulky external high-Q inductors to extend the damping duration while inducing excessive device voltage stress during MPPT. This talk will focus on the discussion of capacitive PEH interfaces for flipping the PEH voltage for energy extraction improvement. It will first cover the basic operations of capacitive PEH interfaces and provide the fundamental analysis on its performance limits. The design tradeoffs between the achievable extracted energy and the different loss mechanisms will be outlined. System level implementation of maximum power point tracking (MPPT) will also be discussed.

The recent wireless sensing and emerging Internet-of-Thing (IoT) market have enabled the development of miniaturized systems with different application requirements. While highly efficient power management is mandatory to ensure the system performance and operation lifetime, on-chip inductive power converters generally exhibits increased manufacturing cost despite of their higher achievable power densities. Due to the full integration together with high energy efficiency and adaptability, reconfigurable switched-capacitor (SC) DC-DC converters are promising for ultra-compact on-chip power solutions. This talk will first cover the basic operations and control methodologies of SC DC-DC converters. It will then introduce the conventional SC DC-DC topologies, followed by the fundamental analyses and different loss mechanisms. Advanced reconfigurable SC DC-DC converters capable of systematic multiple rational voltage conversion ratio (VCR) generation and their fundamental limits will also be proposed, and further compared with the state-of-the-art. Adaptive gate driving techniques with consistent switch driving voltage while preventing reversion loss under wide voltage dynamics will also be introduced. These techniques enable highly efficient SC power converters with better SoC integration for next generation ultra-compact low-cost IoT devices.

Ultra-low power/energy efficient wireless sensing microsystems plays an important role in the upcoming internet of things (IoT) era. Temperature is one of the most common physical parameters. Consequently, high performance CMOS temperature sensors become an important design element of many microsystems. Apart from that, temperature compensation for other kinds of sensors is also widely employed due to the intrinsic temperature dependence in many commercially available sensors. Due to the application considerations, these systems are usually miniaturized with limited battery storage, and some (e.g. passive RFID) maybe even battery-less for further production/maintenance cost reduction. Consequently, it is challenging to achieve ultra-low power which can be in the order of μW to even nW, while achieving high accuracy without elaborate calibration efforts. Apart from that, good supply immunity is also necessary to ensure accurate sensing under significant supply noise. This seminar will first review the system level requirements of passive RFID, followed by the introduction of the fundamentals and operating principles of CMOS temperature sensors using different sensing devices. The main sources of inaccuracy will be identified, followed by possible circuit/system level solutions to achieve high power/energy efficiencies. Different case studies of state-of-the-art CMOS temperature sensors will also be introduced.

Common-mode rejection ratio (CMRR) is a fundamental consideration in the design of instrumentation amplifiers (IA). This talk studies the CMRR consideration with focus on the enhancement techniques. For AC-coupled IAs, the CMRR is often dominated by the mismatch of passive components, which can be improved by a modified chopping structure and impedance trimming. Theoretically, by cancelling the CM current, the CMRR can be improved structurally. The idea can be realized with a dedicated CM loop which replicates the input CM voltage along with the DM path, eliminating the generation of CM current. Moreover, the input CM impedance is improved simultaneously due to the elimination of CM current, which is typically required by IAs interfacing with high-impedance sensors, e.g., dry-contacted electrodes, accelerometers, etc. Demonstrated IA design examples are discussed.

Power-supply noise (PSN) is a key consideration that determines the performance as well as functionality of ICs, especially for modern SoCs with significantly increased scale, level of integration and driving complexity with sophisticated voltage and power controls. Externally measured PSN is inevitably distorted by packaging, PCB, etc., therefore, on-chip or on-die measurement of PSN is highly demanded with large bandwidth, high accuracy and high frequency resolution, which is extremely challenging. Moreover, clean supply is not available in this scenario. This talk overviews the on-chip PSN analyzer techniques, where the subsampling-based approach is promising due to the relaxed bandwidth constraints. However, the accuracy and frequency resolution are fundamentally determined by the number of averaging points, resulting in long measurement time. Multi-slice architecture, time-based quantizer and compressed sensing techniques are discussed with a 20GHz PSN analyzer design example, where significantly improved measurement accuracy and speed are demonstrated in addition to the system scalability.

Design of integrated circuits under near-/sub-threshold supply voltages is driven by the continued technology scaling as well as the increased demand on energy efficiency. Comparing with digital design that can often be compensated from system level, subthreshold analog design relies more on circuit-level techniques. This talk overviews the state-of-the-art subthreshold analog design techniques. Low-voltage design considerations are discussed along with several 0.1V-0.3V OTA and ADC examples. An evolutionary approach from matured amplifier topologies to inverter-based implementation is presented, which has been exploited and demonstrated in the design of near- and/or sub-threshold amplifiers, regulators, integrators and ΔΣ modulators. The potential of time-domain signaling in low-voltage design is also discussed.

SAR ADCs are coming of age due to the mostly digital implementations where the benefit of advanced CMOS technologies can be generally brought into ADC designs. Time-domain signaling is also promising since the speed and time resolution are both scaling favorable. Therefore, the SAR ADCs with time-based comparator have attracted significant interest in recent years. Nevertheless, comparing with oversampled converters where the unique property of VCO, the first-order noise shaping, has been used to enhance the system, Nyquist converters uses only the bit decision of time-base comparison. This talk introduces the concept of oscillation-cycle information in VCO-based comparators. With rigorous analysis, the number of oscillation cycles (NOC) can be generally exploited as a parallel coarse quantization with a large signal, and/or as a quantitative indication of metastability with a small signal. Moreover, the NOC is inherent and of little cost in hardware, power and area. The demonstrated VCO ADCs exhibit significantly enhanced linearity and robustness, comparing with their voltage-domain counterparts. This talk discusses also a closed-form metastability analysis of VCO-based comparator, introducing the metastability depth as a quantitative measure of metastability.

Facing a growing number of patients with neurological disorders, there are only limited therapeutic pharmacological measures which provide only temporary and mild amelioration of the devastating symptoms of these disorders. The use of electrical stimulation of the brain is a treatment option for patients with severe treatment-resistant disorders. Current deep-brain stimulation (DBS) approaches are hindered by inadequate technology that is low-precision and bulky, power-inefficient, and of limited diagnostic utility. The seminar will discuss a high-precision implantable neurotechnology for closed-loop neuromodulation of functional networks of the human brain. Key features of the technology are: 1) sensing from a high number of channels, 2) sensing concurrent with stimulation for true closed-loop operation, and 3) real-time secure wireless data telemetry. The proposed neurotechnology could revolutionize brain therapies in efficacy, size and cost of medical implants.

Technology scaling is power-limited, so compute energy efficiency improvements have to come from chip and system architectures. Increasing application diversity also argues for a more flexible compute architectures, further emphasizing the need for energy efficient design methods. This includes not just chips, but system solutions and dealing with miniaturization and complexity considerations. This talk will therefore discuss design methods for digital chip and system design, provide a detailed example of fixed-function accelerator architecture study, discuss several chip examples for baseband communications processing, and discuss system integration techniques ranging from next-generation medical implants to next-generation wafer-scale chip packaging. These applications further reveal opportunities in system-level design automation that would help address design productivity and system assembly challenges.

The power generation of transistors drops as we move to higher frequencies. At the same time, the free space propagation loss increases, demanding more radiated power from the system. The loss of passive elements in the circuit increases as well, making functions such as oscillation or radiation even more challenging. In order to boost the limited power, multiple sources need to be coupled together in an array structure. However, the significant loss of the coupling circuitry and phase shifters at mm-wave and terahertz frequencies hinders the implementation of large and efficient radiator and phased arrays. Scalable standing wave array structures are proposed based on efficient low-loss coupling schemes in order to boost the power and operation bandwidth. Furthermore, we present a practical approach to maximize Equivalent Isotropic Radiated Power (EIRP) of the source by optimizing influential parameters of the radiation apparatus. Finally, we demonstrate a new phase shifting method based on combining standing and traveling waves and show how it can achieve significantly higher phase shifting range and bandwidth.  Using all these methods we present coupled-oscillators, scalable radiator arrays, and phased arrays with record beam steering range, tuning range, and output power among relevant published works at mm-wave and terahertz frequencies.

In recent years many new mm-wave applications and standards have been emerging. These systems are mostly a response to the ever-growing demand for higher data speed, higher image resolution, and better sensing systems. The same trajectory to THz and higher frequencies will likely to continue in future for higher performance systems. Therefore, it is vital to understand the limit and capabilities of the fabrication platforms specially when the operating frequencies are getting close to or even surpassing the maximum oscillation frequency (fmax) of the transistors. In this talk we will discuss and present three transistor limits for oscillation frequency, harmonic generation, and power amplification. Using these analyses, we have implemented oscillators and amplifiers with record breaking DC-to-RF efficiency and output power at mm-wave and THz frequencies.

Accurate, stable and wideband mm-wave and terahertz sources prove to be essential for coherent data link, active sensing, and radar. The high frequency of operation creates major challenges for implementing such sources such as low tuning range and output power of voltage controlled oscillators (VCO), small locking range for injection locked frequency dividers, and in general high noise level and power consumption of frequency synthesizers. We present a mode switching technique to significantly increase the tuning range of the VCO’s at 200GHz and above. Moreover, a Colpitts-based active varactor (CAV) and a frequency divider with three-phase injection are proposed to reduce the effective loss of the varactors and increase the tuning range of the VCO combined with the frequency divider at 300GHz. Finally, a frequency lock detector is presented for sub-sampling PLL’s that avoids high-frequency dividers, and results in significantly lower power consumption at mm-wave frequencies. Applying these ideas, we demonstrate record breaking VCO’s and frequency synthesizers operating at 40, 200, and 300GHz.

Thanks to the tremendous advances and success of deep neural networks (DNNs), computer architecture research has been booming and enjoying its "Golden Age" recently: a lot of architectural proposals have been proposed for the accelerated execution of the inference or training of DNNs, especially at the edge. Most of them have common architectural features: i.e., hardware-oriented, reconfigurable, domain-specific, and in/near-memory. This talk will try to provide insights on why they are happening and what are the recent findings by showcasing recent research activities mostly in my group.

Neural interface technologies stand to revolutionize disease care for patients with neurological conditions and in the future, the human experience. Today, implantable neurostimulation devices have seen widespread adoption in the treatment of Parkinson’s disease, OCD, epilepsy, and more. Clinical neurostimulators have few channels and provide simple electrical pulses that are programmed by a doctor in a process that can take months or even years. In this talk I will present WAND: Wireless, Artifact-free Neuromodulation Device, which combines high channel count neural recording with stimulation in a truly closed-loop manner for the first time. This technology, enabled by advances in integrated circuit design, will enable patient-specific therapies that will result in improved outcomes and reduced side effects and pave a path to bidirectional brain-machine interfacing. I will also present recent research in a new class of ultrasound-powered interfaces that has enabled us to scale complete wireless neurosensing and neurostimulation devices to volumes below 1mm³, enabling minimally invasive implantation and safe, chronic use inside the human body.

IC chips are key enablers of densely networked smart society and need to be more compliant to security and safety. The talk will start from Electromagnetic Compatibility (EMC) techniques of IC chips on the safety side, toward EMC aware design, analysis and implementation. Then, the challenges will be discussed about the deployment of EMC techniques in the design of IC chips for the higher level of hardware security. Design and simulation techniques of crypto-based secure IC chips with countermeasures for side-channel attacks will also be discussed.

Interactions of IC chips and packaging structures differentiate the electronic performance of power delivery networks (PDNs) in traditional 2D and advanced 2.5D and 3D technologies. This presentation discusses their impacts on signal integrity (SI), power integrity (PI), electromagnetic compatibility (EMC) and electrostatic discharge protection (ESD), through in-depth Si experiments with in-place noise measurements and full-chip level noise simulations. Test vehicles under study are given in traditional 2D face up and flip chip packaging, 2.5D fan-out wafer level packaging (FOWLP), and 3D chip stacking with through silicon vias (TSVs).

Hardware security, application of modern digital cryptography and authentication technologies for protecting information in electronics, involves analog functionality to avoid physical threats in operation fields. This presentation provides an overview with historical aspects of on-chip physical attack protection circuits and assembly structures for the detection and disablement of malicious attempts on cryptographic devices. Design examples to combat passive and active side channel attacks as well as hardware Trojans are discussed and demonstrated with test vehicles.

Noise coupling in RF system-on-chip integration is studied by on-chip and on-board measurements as well as by concatenated simulations at chip and system levels. Integrated power and substrate noise simulation techniques use chip-package-system board combined circuit models and verify noise coupling in mixed analog-digital integration. Wireless system level simulation evaluates the impacts of coupled RF noises on wireless performance through metrics of throughput and error vector magnitude (EVM). In addition, post-silicon techniques at packaging and assembly stages are potential options to mitigate RF noise coupling problems. The presentation will also include demonstrations with test vehicles.

We have developed a CMOS image sensor with an organic photoconductive film (OPF) laminated on pixel circuits, different from those of a conventional silicon image sensors, in which the organic thin film for photoelectric conversion and the charge storage part for signal charge accumulation are completely independent. In this presentation, we focus on the advantageous features of the OPF image sensor; [1] technology that realizes over 120 dB simultaneous-capture wide dynamic range; [2] global shutter technology achieving high saturation signals per unit square that is 10 dB higher than that of silicon image sensors with the global shutter function, without sacrificing pixel area; [3] RGB-NIR sensor technology capable of controlling NIR sensitivity by simply controlling the voltage applied to the OPF. Moreover, we introduce about 8K4K high resolution sensor technologies with 60fps high frame rate, 450ke- high saturation signals, and the global shutter function at the same time. We believe these features of the OPF image sensor will contribute to leaps in the imaging and sensing fields.

System behavior and performance of power management strongly depend on the implementation on circuit level. This tutorial covers the design of DCDC converter building blocks like power switches, gate drivers and their supply, level shifters, error amplifier as well as control loop and current sensing techniques. Circuits for diagnostics and protection will also be addressed. Increasing switching frequency scales down passive components, but poses a challenge for the design of timing critical circuits. The lecture will highlight trade-offs between speed, efficiency, complexity, voltage and current capabilities, etc.

Efficient conversion of energy is one of the megatrends, enabled by advanced semiconductors and microelectronics. As a wide-band gap material, GaN (gallium nitride) offers a huge potential to reduce the overall power electronics system size and cost. However, parameters such as common-mode transient immunity (CMTI) and minimum parasitic gate loop inductance become more challenging, as they degrade the fast-switching performance. This lecture presents design aspects on system and circuit level related to GaN. The concept of high-voltage energy storing (HVES) enables highly integrated gate driver designs, which can even utilize the parasitic gate loop inductance for a resonant gate drive approach. Monolithic GaN-on-Si integration reduces the gate loop inductance nearly to zero and allows for integration of a full power converter including a fully integrated control loop on a single die. A self-supplied 400V 15W offline buck converter GaN-IC will be discussed with which achieves superior efficiency and power density along with lowest component count. Original analog circuits in GaN are presented such as nmos-only auto-zero comparator and high voltage supply regulator.

Power Management has significant impact on the overall system size and cost of systems-on-chip. Multi-MHz DCDC converters enable highly integrated power management solutions. Automotive and server applications are supplied by nominally 12V with a trend for higher supply voltages towards 48V. Hence, converters with high conversion ratio are required to supply CPUs, MCUs, RAM, etc. This talk addresses the challenges on system and circuit design level for highly integrated, fast switching point-of-load converters, including power stage design, high resolution dead time control and soft-switching.

Power management comprises integrated circuits for highly efficient power supplies and for controlling power switches. These have recently gained tremendous importance in order to make electronic solutions for global growth areas such as renewable energies, autonomous driving and biomedical more compact, more energy-efficient and more reliable. Future applications in the field of machine learning and AI will only be possible with intelligent power management to supply complex processors and sensors. This talk gives an overview at system and circuit level of current and future challenges, along with examples including the topics of automotive, wearables, GaN, and current measurement.