Distinguished Lecturer Roster

This lecture focuses on a recently proposed technique in the art of radio receiver design, where the channel-select filter and the ΔΣ-based A/D converter are merged into a single function, the filtering A/D converter, improving power consumption and area occupation. A number of different implementations of the filtering A/D converter will be discussed, together with their strengths and weaknesses.

This presentation goes through the fundamentals of harmonic oscillators integrated in CMOS processes, starting with basic linear and non-linear circuit analysis and continuing with a rigorous yet intuitive time-variant theory of phase noise. A recently proposed, alternative theory of phase noise, capable of powerful predictions, will be discussed as well, and the phase noise performance of the most popular harmonic oscillators will be derived.

As one of the truly fundamental analog functions in any wireless/wireline application, the voltage-controlled oscillator keeps attracting a great deal of well-deserved attention. In this presentation, we will briefly discuss the mechanisms of phase noise generation in harmonic oscillators, after which we will analyze both classical and emergent oscillator architectures, describing pros and cons for each. Finally, we will examine various techniques to achieve a very wide oscillator tuning range.

Functional near-infrared spectroscopy (fNIRS) is an effective and non-invasive functional brain imaging method. Neuronal activities of the brain are strongly coupled with the hemodynamics in the local cerebral cortex and the hemodynamics can be extracted by using the fact that the absorption spectra of oxy hemoglobin (HbO) and deoxy hemoglobin (HbR) differs in the near-infrared region of the spectrum. The fNIRS retrieves the hemodynamics by monitoring the variations in the optical signal power traveling through the cerebral cortex of the brain. The fNIRS has an apparent advantage over functional magnetic resonant imaging (fMRI) in terms of cost and portability. However, the inherent limitation of the spatial resolution of the fNIRS restricts its widespread use in clinical applications. In addition, the conventional fNIRS devices have yet to utilize its potential for portability to the fullest extent. In this talk, an ASIC-based highly portable real-time brain-imaging system with 4mm spatial resolution will be presented. The technical improvements are achieved by joint optimization of hemodynamic extraction algorithm and high-SNR circuitry.  

The ever-increasing demand for bandwidth triggered by mobile and video Internet traffic requires advanced interconnect solutions satisfying functional and economic constraints. Optical solutions are generally believed to replace high-speed conductor-based interconnects even in short-reach links. However, the widespread use of optical communication systems in high-volume short-reach applications is yet to gain acceptance due to its high-cost components, high-precision manufacturing process requiring micron-level accuracy, and the sheer physical size of modules. Moreover, designs with a practical balance of performance/robustness/power consumption of optical devices erode the potential advantage of the optical fibres. This being the case, the E-TUBE proposes a new interconnect scheme suitable for next-generation high-speed I/O interfaces. The E-TUBE demonstrates an unprecedented level of performance in terms of bandwidth per carrier frequency, power and density without requiring a precision manufacturing process. The E-TUBE exhibits a frequency-independent loss-profile of <4dB/m and has >20-GHz bandwidth over the V band. A single-sideband signal transmission enabled by the inherent frequency response of the E-TUBE renders two-times data throughput without any physical overhead compared to conventional radio frequency communication technologies. Increased centre frequency accompanied by semiconductor technology scaling will result in the increase of wire density and throughput. In addition, frequency-independent loss-profile of the E-TUBE enables the adoption of advanced modulation schemes that improve the spectral efficiency without complex equalizers. Transmission up to 14Gb/s signals over 1.2m has been tested using 73GHz carrier frequency (fC). The IC is fabricated in 40nm CMOS and the figure-of-merit of the interface is 0.52J/b/m×fC (Radio frequency circuits only: 0.3J/b/m×fC).  

The steady growth in demand for bandwidth has triggered the implementation of >100Gb/s wireline communication systems. Such high-speed systems suffer from impairments such as channel dispersion, noise, and process nonidealities. In addition, tight power budget in transceiver ICs required for high port density makes the IC design even more difficult. Under such circumstance, relentless scaling of feature sizes exemplified by Moor’s law has enabled the application of sophisticated signal processing techniques to overcome aforementioned problems while satisfying stringent power budget. In this talk, high-speed low-power broadband digital CMOS transceiver design techniques are presented. Moreover, practical 100Gb/s transceiver design examples satisfying all the stringent and complex specifications while mitigating inherent circuit level issues are covered. Diverse technical innovations lead to significant reduction in the power consumption, which contributes towards the implementation of green datacenters. 

High-entropy randomness is the bedrock of secure platforms, providing encryption keys for secure communications and media content protection as well as generating unique IDs for digital identity.  Two forms of entropy are required in secure systems today: (i) dynamic entropy in the form of time-variant encryption keys and session IDs, and (ii) static entropy in the form of stable, repeatable device-unique keys, chip IDs, and digital fingerprints. True Random Number Generators (TRNGs) and Physically Unclonable Functions (PUFs) are the two critical circuits that can be used to generate dynamic and static entropy respectively. TRNGs harvest dynamic entropy from natural physical phenomena such as semiconductor device noise, oxide breakdown or radioactive decay, whereas PUFs harness the variations in semiconductor manufacturing processes to generate a time-invariant ID from nominally identical circuits. We will cover state-of-the-art designs of TRNGs and PUF circuits in advanced high-volume manufacturing.

Future computing systems spanning exascale supercomputers to wearable devices demand orders of magnitude improvements in energy efficiency while providing desired performance. The system-on-chip (SoC) designs need to span a wide range of performance and power across diverse platforms and workloads. The designs must achieve robust near-threshold-voltage (NTV) operation in nanoscale CMOS  process while supporting a wide voltage-frequency operating range with  minimal impact on die cost. We will discuss circuit and design technologies to overcome the challenges posed by device parameter variations, supply noises, temperature excursions, aging-induced degradations, workload and activity changes, and reliability considerations. The major pillars of energy-efficient SoC designs are: (1) circuit/design optimizations for fine-grain multi-voltage & wide dynamic range, (2) fine-grain on-die power delivery & management, (3) dynamic adaptation & reconfiguration, (4) dynamic on-die error detection & correction, and (5) efficient interconnects.

Many-core SoC spanning clients to servers to high-performance computing systems in scaled CMOS process are discussed. Key circuits and design techniques that enable a wide dynamic voltage-frequency operating range, spanning multi-threaded high-throughput near-threshold voltage (NTV) to single-threaded burst performance modes, are elucidated. Fine-grain multi-voltage design and spatio-temporal power management schemes to achieve maximum performance under stringent thermal and energy constraints are presented, along with integrated voltage regulator technologies. Real chip design examples are used to illustrate basic design principles and practical considerations.

The scalability of CMOS technology has driven computation into a diverse range of applications across the power consumption, performance and size spectra. Today Data Center (DC) and High Performance Computing (HPC) performance is increasingly limited by interconnection bandwidth. Maintaining continued aggregate bandwidth growth without overwhelming the power budget for these large scale computing systems and data centers is paramount. The historic power efficiency gains via CMOS technology scaling for such interconnects have rolled off over the past decade, and new low-cost approaches are necessary. In this talk a number of promising solutions including Silicon-Photonic-based interconnects that can overcome these challenges will be discussed.  In particular effective co-design of electronics and photonics as a holistic approach for reducing the total power consumption and enhancing the performance of the link will be presented. 

Wearable and implantable medical devices can enable new approaches to the diagnosis and treatment of human diseases. Design and implementation of sensors and neural interfaces that are non-invasive or minimally invasive are essential for viability of such devices. In this talk we will focus on miniaturized devices that are wireless and highly energy-efficient. First an ultra-low-power sensor for continuous measurement of glucose and lactate will be presented. This minimally invasive wireless device can be injected just under the skin, and designed to have high dynamic range and high resolution. In the second example, we introduce a closed-loop neural interface for seizure detection and prevention. In this project, hardware efficient classification and feature extraction techniques are utilized to enhance the performance and energy-efficiency of the system. 

Full duplex wireless is an exciting emergent wireless communication paradigm where the transmitter and the receiver operate at the same time and at the same frequency. Full duplex potentially immediately doubles wireless capacity at the physical layer, while offering greater flexibility and other benefits at the network layer. However, the fundamental challenge associated with full duplex is the tremendous transmitter self interference at the receiver that can be a billion to a trillion times more powerful than the desired signal. This presentation covers recent advances in the design of integrated RF and millimeter-wave full-duplex transceivers with self-interference cancellation in various domains – antenna, RF, analog baseband and digital. This presentation will also cover developments from the Columbia FlexICoN project (http://flexicon.ee.columbia.edu), which is investigating network-layer implications of full duplex, cross-layering in full duplex networks and co-development of the physical layer and the network layer.

There has been a renewed interest in millimeter-waves in the recent past for next-generation (5G) wireless communication networks. While millimeter-wave silicon systems-on-chip (SoCs) are a mature technology, there are several open challenges, including the generation of high output power to close link budgets over distances exceeding 100s of meters, and the implementation of energy-efficient millimeter-wave systems. This talk will cover recent research on stacked millimeter-wave CMOS power amplifiers with high efficiencies, watt-class millimeter-wave CMOS PAs, highly digital millimeter-wave transmitters, and large-scale millimeter-wave arrays. Finally, this talk will contemplate advanced wireless communication paradigms at millimeter-waves, including massive MIMO.

Lorentz reciprocity is a fundamental property of linear time-invariant passive circuits and systems constructed from conventional materials. However, non-reciprocal components, such as circulators, enable new wireless communication paradigms, such as full duplex wireless. Conventionally, non-reciprocal circulators have been realized using ferrite materials that exhibit the magneto-optic Faraday effect, and are consequently incompatible with CMOS, bulky, and expensive. Recent research has shown that reciprocity can be broken and non-reciprocal circulators can be built in CMOS using linear periodically time-varying (LPTV) circuits. This represents an interesting and unique property of LPTV circuits beyond the traditionally exploited tunable high-quality filtering in the so-called “N-path filters”. We will describe the fundamental physical principles from our recent 2016 Nature Communications paper, as well as three generations of CMOS circulators and circulator-based wireless systems published in ISSCC 2016 and ISSCC 2017 that target emerging full-duplex and 5G millimeter-wave applications.

Reconfigurable/broadband RF radios must operate in the presence of increased interference, either from the same platform or from the environment, due to the absence of agile front-end filter technology. This talk will cover various techniques for interference mitigation in the transmitter, receiver and synthesizer domains for both FDD/co-existence and unknown interference scenarios. For the former, low-noise active cancellation of transmitter leakage in receivers, and mixed-domain FIR filtering of out-of-band noise in digital RF transmitters will be discussed.  For unknown interference, all-passive higher-order N-path filters and spatio-spectral interference mitigation in RF receiver arrays will be covered. On the synthesizer front, I will describe an instantaneous-hopping RF synthesizer that enables interference avoidance. 

Linear periodically time-varying (LPTV) circuits have drawn tremendous research interest in the recent past due to the ability to realize tunable high-Q filters on chip through the so-called “N-path filters”. However, more recently, new functionalities of LPTV circuits have been investigated, including equalization at RF for wideband interference cancellation, construction of non-reciprocal components, and impedance-domain beam forming and beam nulling at RF in multiple antenna systems. This talk will first cover new and intuitively appealing theoretical formulations for LPTV circuits, and then will describe these new functionalities in detail, from theory to implementation.

The aim of point-of-use biological/chemical diagnostics is to transform the traditional bulky laboratory instruments into handheld total analysis systems, bringing down the cost, size and sample-use by orders of magnitude. An Nuclear Magnetic Resonance (NMR) CMOS transceiver enables repeatable, versatile and low cost screening of samples as it is label-/washing-free, and immobilization-free for the electrodes. Herein, two lab-on-CMOS NMR systems are presented: the first facilitates multi-step multi-sample management by electronic-automated digital microfluidics, whereas the second benefits from magnetic-field stabilization and thermal management to unify multi-type assays (target detection, protein state analysis and solvent-polymer dynamics) in a handheld scale suitable for healthcare, food industry and colloidal applications. The detection limit is <100pM for E. faecalis derived DNA. The platform consumes 120x less sample, and is 96x lighter and 175x smaller than a commercial product.

With more and more frequency bands defined globally in the sub-6GHz spectrum, multi-band software-defined front-end modules (FEMs) and SAW-less radios will play a key role towards an affordable 5G. This lecture starts with the multi-band SAW-less receivers enabled by a variety of N-path mixing/filtering techniques. One key idea - gain-boosted N-path filtering - is then developed to realize a compact multi-band SAW-less transceiver. Unlike the typical zero-IF transmitter and receiver that the functions are arranged in an open-loop style, our new transceiver unifies the signal amplification, high-Q bandpass filtering and I/Q (de)modulation in a closed-loop formation, rejecting the out-of-band (OOB) noise in the transmitter mode, and OOB blockers in the receiver mode. Finally, large-signal-handling N-path LNAs for FDD-LTE and diversity 3G/4G receivers will be discussed.

Ultra-low-power (ULP) radios are the key element of a wide variety of Internet-of-Things (IoT) products. This lecture starts with the system aspects of different radio architectures, then reviews the pros and cons of different state-of-the-art ULP RF techniques such as current-reuse, function-reuse and ultra-low-voltage. Their suitability for different single-/multi-band standards such as Bluetooth Low Energy, ZigBee and NB-IoT will also be discussed. Toward self-powering by the environments, the opportunity of using energy-harvesting sources such as thermal, light and vibration will also be presented. State-of-the-art industrial radios will serve as the basis to underline the current achievements and project the future challenges.

3D imaging has become a hot research topic in the last few years, driven by the needs of emerging markets looking for next-generation user interfaces based on gesture control. Moreover, 3D vision systems offer amazing possibilities of improvement in many other areas like self-driving cars, security and surveillance, cultural heritage preservation, ambient-assisted living, industrial control, etc., because they significantly increase the robustness of object classification with respect to conventional 2D imagers. This lecture will introduce participants to the exciting field of 3D imaging, providing an overview about image-sensor architectures capable of distance measurement. An introduction to existing 3D imaging technologies will be given, addressing the peculiarities of each measuring technique and the possible application domains. The focus is on solid-state sensor architectures as enabling technologies to improve the performance of 3D vision systems, with a particular emphasis on time-of- flight implementations. Finally, participants will get some practical tools such as figure of merits and experimental characterizations guidelines for a comprehensive comparison of 3D imager performance and a perspective toward the future challenges in this fast-evolving field. 

There are many scientific imaging applications where image sensors exhibiting extremely high sensitivity and sub-nanosecond timing resolution are needed, among them Positron-Emission Tomography, Fluorescence Lifetime Imaging (FLIM), and Raman spectroscopy. This lecture presents the theory and circuit architectures necessary to realize CMOS image sensors with single-photon detection sensitivity, by analysing and comparing the available options. Ultra-low-noise readout circuit architectures adopted in state-of-the-art sub-electron imagers based on conventional photodiodes will be described together with an overview of the emerging field of CMOS single-photon avalanche detectors. Design methodology will be included to investigate the circuit optimization through case studies taken from the state-of-the-art in this domain.

CMOS Single Photon Avalanche Diode (SPAD) arrays are emerging as appealing solid-state detectors in imaging applications where high sensitivity and extremely good timing resolution are required. This lecture will provide an overview of SPAD detectors design in CMOS technology addressing the main figure of merits, their characterisation methodology and analysing all the pros and cons of this fast-growing technology platform. The required front-end and processing readout circuits will be presented covering the most interesting sensor architectures proposed in the literature for time-resolved imaging applications from biomedical to LIDAR.

Cell and brain interfacing has gained a lot of interest in recent years. Thanks to advancements in technology scaling, current state-of-the-art systems are able to record the electrical activity down to single neuron resolution from several hundreds of recordings sites at the same time. This is a critical tool for neuroscientist to help understand how our brain operates. In recent years also stimulation has gained a lot of interest. Neural stimulation serves a lot of potential applications like restoring bodily functions for disabled people, suppressing pain, brain-computer-interfaces and Parkinson’s disease. This tutorial will focus on the circuit techniques and technologies to enable such high-density neural recording and stimulation. It will go from high-level system design aspects, to processing/technology aspects (electrodes) and will end with specific circuit design techniques.

This lecture will cover the basics of measuring ExG (with a primary focus on ECG) on the human body. The measuring method and important effects like mains interference, electrode impedance will be explained. An overview of common instrumentation amplifier architectures and design examples will be given. The lecture will also talk about common design techniques often employed in biomedical instrumentation amplifier design like chopping, DC-servo loops and impedance boosting.

While IoE spans very diverse and broad application domains, a lot of those require extensive sensing. Individual nodes in the IoE can be equipped with a multitude of quite diverse sensors like gas, temperature, humidity, pressure, position and various biomedical sensors. Area-efficient, high-performance and low-power sensor interface design is thus an important prerequisite for successful deployment of IoE. This short course will address exactly these topics. A brief overview of various sensor types and how to interface them will be discussed. The unique design challenges for sensor interfaces will be addressed. The short course will discuss in-depth state-of-the-art instrumentation amplifier designs as well as trans-impedance amplifier designs both of which are at the heart of a lot of sensor interfaces. Advanced circuit design techniques like chopping, bootstrapping, offset cancellation will be explained. Finally a look into novel and promising research areas like time-domain sensor interface design will conclude the short course.

This lecture will focus on general trends and promising applications in the field of wearable healthcare and tele-monitoring. The application needs will be linked towards custom ASIC requirements and some state-of-the-art implementations will be shown and discussed.

Biology provides us with fascinating examples of intelligent, low power, and highly efficient sensory systems.  With the advances in CMOS technology, it has become feasible to build microelectronic systems that mimic some of the key features found in biology. 
This talk will focus on CMOS vision sensors for polarization imaging. We will review briefly the concepts of polarization and how it is used by various species in nature to enhance their vision or to aid with navigation and communication.
Inspired by the biology we have explored polarization for a variety of applications to detect features that are hard to see or even invisible to the human eye. More recent results from the literature including the use of polarization imaging for disease detection will be reviewed. Motivated by the potential advantages of polarization imaging, we have developed a CMOS imager that combines the pixel array with micropolarizers and on-chip processing. Details of the design and polarizer optimization will be described.

This presentation will explore fully digital architectures and circuit topologies for future wireless backhaul systems with aggregate data rates comparable to those of future 64Gbaud fiberoptic systems. The main features of FD-SOI CMOS technology and how to efficiently use its unique features for RF and mm-wave SoCs will be reviewed first. We will discuss the impact of the back-gate bias on the measured I-V, transconductance, fT and fMAX characteristics and compare the MAG of FDSOI MOSFETs with those of planar bulk CMOS, SOI and SiGe BiCMOS transistors through measurements up to 325 GHz. I will provide examples of FDSOI LNA, mixer, switches, and PA circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of sub-28nm CMOS technologies. Examples of measured 45nm SOI CMOS digital transmitters with free space constellation formation at 100 GHz and 140 GHz will be provided along with a 1-30GHz fully digital I-Q transmitter with 20 dBm output power for 5G terminals. Finally,  Predistortion and spectral shaping techniques in the transmitter, and receiver ADC-based equalization at 64 GBaud will be discussed.

In this presentation I will review the specification for 56Gbaud and 128Gbaud ‎transmitter electronics as required for driving large-swing optical modulators. Two possible transmitter implementations will be considered: (ii) based on sub-28nm CMOS DACs followed by a large swing (>5Vpp differential) linear driver in SOI CMOS, SiGe BiCMOS or III-V technology and (ii) based on large-swing power DACs in SiGe BiCMOS and InP HBT technology. Practical implementations of linear large-swing drivers and power DACs at 64GBaud and 120 GBaud will be shown.

This presentation will compare the high frequency performance scaling of SiGe HBTs and MOSFETs to 2-3nm gate length and beyond 2THz transistor fMAX based on technology CAD (TCAD) and atomistic simulations. Characterization techniques and S-parameter measurements of state-of-the-art silicon MOSFETs, SiGe HBTs, and of a variety of HBT-HBT and for  MOS-HBT cascodes from DC to 325 GHz will be discussed along with simulations of the scaling of analog and mixed-signal mm-wave benchmark circuit performance from the current to future technology nodes. Finally, we will take a look at the room-temperature operation requirememts for coupled double quantum-dot Si qubits which rely on resonant tunnelling  multiple-gate MOSFET structures with sub-5nm dimensions in all directions.

This talk will cover the requirements, design, and experimental demonstration of two classes of ultra-low-power mm-wave sensors. For a realistic performance comparison, identical circuits were implemented in both 55nm SiGe BiCMOS and 45nm SOI CMOS technologies. The first is a 40mW power consumption multi-channel doppler-radar sensor for touchless gesture control operating in the 60GHz band. The second is a 77GHz active mm-wave tag with built-in wake-up function and BPSK modulation which is intended for operation with an FMCW car radar as the base-station. The circuit topology choices that maximize performance while minimizing power consumption will be contrasted. In the 55nm SiGe BiCMOS multi-channel Doppler sensor, this led to a creative alternation of HBT and CMOS stages in the local oscillator tree.

As mm-wave operating frequencies are relatively close to the cutoff frequency of the active devices, little design freedom is left for the front-end building blocks in mm-wave radios. Furthermore, layout parasitics have more effect at mm-wave frequencies than in the low-GHz range, which has been for a long time the domain of RF CMOS design. As a result, careful modeling at mm-wave frequencies is needed for all components, which slows down the classical RF IC design flow. Furthermore, as impedances at these high operating frequencies get lower and the wavelength on chip is just a few millimeters, on-chip versions of classical discrete microwave components need to be designed such as transmission lines, couplers, splitters, hybrids, ... This talk focuses on the design of 60GHz CMOS low-noise amplifiers and power amplifiers and the passive components that are typically used in these circuits. The design of these blocks will be explained step-by-step. Fundamental metrics for noise, linearity, and impedance matching will be addressed.

The speed increase of CMOS thanks to the downscaling in the past ten years, together with the allocation of unlicensed spectrum around 60 GHz, has given rise to much research worldwide on mm-wave IC design in CMOS. The frequency band between 57 GHz and 66 GHz is intended for high datarate wireless communication using RF bandwidths of more than 1 GHz. The commercial deployment of mm-wave ICs is taking much more time than expected, partially due to the design challenges caused by the high operating frequency, which is more than ten times higher than the commercial ICs for the most widely used wireless communication standards, which operate below 6 GHz. To relax the high path loss at mm-wave frequencies in the link budget of wireless transceivers, these transceivers contain, next to the classical functionality of radios, beamforming functionality. This talk will explain the basics of beamforming together with several implementations of the beamforming control in the analog part of the transceivers. Further, most important bottlenecks of mm-wave radio architectures such as phase noise and power efficiency are addressed and several solutions are discussed.  

The demand for cheap and ubiquitous accurate motion detection sensors for road safety, smart homes and robotics justifies the interest in single-chip mm-wave radars: a high carrier frequency allows for a high angular resolution in a compact multi antenna system and a wide bandwidth allows for a high depth resolution. With the objective of single-chip radar systems, CMOS is the natural candidate to replace SiGe as a leading technology. Compared to the classical pulse-based radar systems, continuous wave (CW) radar systems increase the output energy for a given supply and they require a relatively simple receiver front-end. Intensive digital computation (correlations, accumulations, FFTs, ...) is used to increase processing gain and to extract Doppler information. CW radar systems can use frequency modulation (FMCW) or phase modulation (PMCW). As TX and RX are active simultaneously in the same bandwidth, the limited TX-to-RX isolation yields a spillover that is much higher than the signal that the radar aims to detect.

This talk discusses the CMOS implementation issues of both FMCW and PMCW systems, starting from the system level, which includes some radar basics, down to the circuit level of the analog transmit and receive circuitry.

MEMS inertial sensors, namely accelerometer and gyroscope, can be found in many applications, such as gaming, mobile phones and robots. However, MEMS inertial sensors have not been widely seen in high-end applications, such as inertial navigation. This is mainly due to the stability limitation of the MEMS inertial sensors, arising from various noises in the system. In this talk, I will present a high-performance MEMS gyroscope with a CMOS readout circuit, which demonstrates a sub-0.10/h bias-instability. The talk will focus on the CMOS readout circuit design.

MEMS inertial sensors, namely accelerometer and gyroscope, can be found in many applications, such as gaming, mobile phones and robots. However, they have not been widely seen in high-end applications, such as inertial navigation. This is mainly due to the stability limitation of the MEMS inertial sensors, arising from various noises in the system. In this talk, I will present a high-performance MEMS oscillating accelerometer with a CMOS readout circuit, which demonstrates a sub-mG bias-instability. The talk will focus on the CMOS readout circuit design.

Wearable and implantable medical devices have shown great benefits in monitoring health conditions and combating various diseases that cannot be cured by conventional medical means. The physiological and neural signal acquisition is at the very front end of such devices, and its performance is critical to the overall system. This talk will start with a quick introduction of the neural signal recording, followed by several neural recording amplifier designs, in which different circuit techniques are employed to improve the performance. The talk will conclude with the recent trend in neural signal recording amplifier design.

Chronic diseases account for over 1/3 of deaths around the world. To mitigate the impact of such diseases, healthcare paradigm is now shifting from reactive illness management towards proactive and preemptive health management; the goal here is to maintain a healthy life in the first place or to prevent illness from getting any worse by continuously monitoring health during normal daily life. Body Area Network (BAN) is an attractive means for continuous and pervasive health monitoring, yet its unique and harsh environment gives circuit designers many challenges.  As human body absorbs the majority of RF energy around GHz band, existing RF radio may not be an ideal for communications between and on-body sensors. In order solve the issues, this talk covers two types of BAN: body coupled-based and wired/fabric-based. Body-coupled based BAN utilizes human body itself as a communication medium, where the lecture will begin with channel characteristics, followed by design considerations and transceiver implementation examples. For the wired/fabric based BAN, we will cover several flexible platforms that enable BAN, and discuss what and how circuit designers should consider such non-conventional environments. Low energy circuit techniques to overcome their limitations will also be discussed. We will then will review their various system aspects.

 Wearable healthcare sensor provides attractive opportunities for semiconductor sector. The target here is to mitigate the impact of chronic diseases by providing continuous yet adequate low noise monitoring and analysis of physiological signals. However, the wearable environment is challenging for circuit designers due to its unstable skin-electrode interface to begin with. Wet and dry electrodes have significantly different electrical characteristic that needs to be addressed. Also, in such environment, the trade-off between available resource and performance among the components both in analog front-end and in digital back-end is crucial. This lecture will cover the design strategies of bio interface circuits for such wearable sensors. We will first explore the difficulties, limitations and potential pitfalls in wearable interface and strategies to overcome such issues. After that, system level considerations for better key metrics such as energy efficiency will be introduced. Several state-of-the-art instrumentation amplifiers that emphasize on different parameters will also be discussed. We will then see how the signal analysis part impacts the analog interface circuit design. The lecture will conclude with interesting aspects and opportunities that lie ahead.

Epilepsy is a severe and chronic neurological disorder that affects over 65 million people worldwide. Yet current seizure/epilepsy detection and treatment largely relies on a physician interviewing the subject, which is not effective in infant/children group. Moreover, patient-to-patient and age-to-age variation on seizure pattern makes such detection particularly challenging. To expand the beneficiary group to even infants, and also to effectively adapt to each patient, a wearable form-factor, patient-specific system with machine learning is of crucial. However, the wearable environment is challenging for circuit designers due unstable skin-electrode interface, huge mismatch, and static/dynamic offset.

This lecture will cover the design strategies of patient-specific epilepsy detection System-on-Chip. We will first explore the difficulties, limitations and potential pitfalls in wearable interface circuit design, and strategies to overcome such issues. Starting from a 1 op-amp instrumentation amplifier (IA), we will cover various IA circuit topologies and their key metrics to deal with offset compensation. Several state-of-the-art instrumentation amplifiers that emphasize on different parameters will also be discussed. Moving on, we will cover the feature extraction and the patient-specific classification using Machine Learning technique. Finally, an on-chip epilepsy detection and recording sensor SoC will be presented, which integrates all the components covered during the lecture. The lecture will conclude with interesting aspects and opportunities that lie ahead.

Digitally assisted ADCs have become mainstream. The move to finer geometry processes and the insatiable need for higher resolution ADCs at higher sample rates have made digital assistance a necessity. In this talk, we discuss some of the advanced calibration techniques for high speed and high resolution ADCs. These include techniques to correct for inter-stage gain errors, non-linearity, settling and memory errors. Techniques covered include correlation-based calibration, summing node calibration, split-ADC calibration, reference ADC calibration and statistical-based techniques. The talk will discuss the advantages and limitations of the different approaches, some of the practical considerations and some state-of-the-art and implementation examples.

Pipelined ADCs with their various incarnations continue to occupy a sweet spot in the high-speed and high-performance ADC space. In this session, we cover the fundamentals of pipelined ADCs from the architecture and circuit perspectives. Architecture trade-offs, and key circuit building blocks will be covered.  

For an ADC designer or user, it is imperative to understand the various performance metrics, and their relationship to each other. Since there are multiple dimensions of performance, the characterization of an A/D converter can be a complicated and confusing process. In this talk, we discuss the metrics used to characterize the A/D converter’s performance, their relation to each other, and the manifestations of the various ADC non-idealities.  

Despite the many applications that could substantially benefit from the energy-performance achievable with an SoC implemented in an advanced process technology, the high costs of designing and verifying such an SoC using current methodologies limits their adoption to end markets greater than ~$1B in size. Not only has this prevented substantial hardware innovation in emerging markets, but even in markets large enough to bear the high initial design cost, designers are being put under constant pressure to improve their productivity given increasingly tight time-to-market constraints and product cycles. In this talk, I will describe a collaborative effort to develop an "agile" approach that aims to substantially reduce the design and verification costs of such advanced SoCs. Building on principles originally developed for agile software design, the key missing piece for hardware is that rather than focusing on developing instances, designers should focus on developing generators that facilitate re-use and enable agile validation as well as verification. As I will describe in this talk, to support this shift in approach, our team is developing technologies that enable generation of digital and analog hardware as well as the means to verify the hardware that is produced. After briefly describing each of these technologies and highlighting some of their key features, I will then briefly describe the SoC generator we have developed and used to tape-out multiple SoC demonstrators on TSMC's 16nm FFC process.

In nearly all modern computational applications, the achievable performance is intimately linked to the cost and speed of communication between chips within the system.  For this reason, link data-rates have continued to scale at an aggressive rate (roughly doubling every 4 years), but since the power available for the I/O circuitry tends to remain relatively constant, the energy-efficiency of the transceivers must simultaneously be improved as well.  Although there has been a push to adopt higher-order modulation schemes (PAM4) and ADC-based solutions at the 56Gb/s generation, these techniques typically result in higher power budgets and/or high latency (due to the use of error correcting codes).  In order to explore the ultimate efficiency limits, my group has therefore focused on mixed-signal NRZ solutions, and in this talk I will describe the circuit and link architecture optimizations that allowed us to realize a complete 60Gb/s transceiver supporting communication over a 0.7m twin-ax cable (~21dB loss at 30GHz) while dissipating only 288mW in a 65nm CMOS process.     

Current and future hardware products are strongly driven by their interfaces (both in terms of sensing/actuation as well as communications), and since all such interfaces must deal with the analog nature of the real world, these products must typically integrate substantial analog functionality. However, the level of analog designer productivity has not really improved along with silicon technology scaling, and for modern processes in particular, have perhaps even taken a step backwards due to dramatic changes in the physical layout design rules. Therefore, if we are to have any chance of addressing the NRE barrier to custom hardware design, we must also address the analog design productivity gap. In this talk I will present our efforts that aim to close this gap by injecting ideas inspired by agile software devleopment into the analog design paradigm. In particular, we have developed an open-source framework called the Berkeley Analog Generator (BAG) that enables analog designers to codify their design approach (i.e., the steps they took to convert a set of inputs specifications into a fabricate-able design) in an executable generator. In this paradigm, rather than delivering a particular instance (i.e., a point design with a given set of specs), analog designers should focus their efforts on the development of these generators. We have successfully practiced this approach on a variety of technologies and analog blocks, and the results from those endeavors will be highlighted throughout the talk.

Systems-on-Chip (SoCs) have been a reality in the past 15 years. Several dozens of Different Functional blocks are being integrated on a single die, reaching transistor counts of over a billion. From the Analog portion of an SoC the Data Converters are probably the most challenging blocks, often limiting system performance and dominating power dissipation. However, requirements regarding yield, die-size, scalability, noise immunity, power and the fact That logic is almost for free, cause distinct differences between embedded Data Converters and their stand-alone, usually general purpose, counterparts. The presentation describes these differences and provides an overview of the state-of-the-art in embedded Data Conversion.

In large SoC’s Data Converters take a dominant position both from a performance Point of view as well as from an energy consumption point of view. The past two decades have shown a strongly intensified search for more power efficient Data Converters, in particular power efficient Analog-to-Digital converters. This presentation will focus on power efficiency of Nyquist-rate Analog to Digital converters and discuss what has been proposed in open literature to reduce the energy consumption, both from a circuit point of view as well as from an architectural point of view. To get a good grasp of how circuit and architectural choices affect the power consumption, a method will be introduced that allows a quick estimation of the power consumption of an ADC, based on the required SNDR, the sampling frequency, the used technology as well as the chosen ADC architecture and circuit implementations. The proposed method enables a comparison based on these choices and can show what their impact is on the power efficiency, without going through the elaborate design of several architectures. It also shows which recent inventions made a large impact on power efficiency and how these inventions can also be of use in other architectures than the ones they have been introduced in.

Introduction to high-speed current-steering DACs. The principle of current-steering DACs is extremely simple and a good designer needs to know all error mechanisms. Common error mechanisms will be discussed, with error sources affecting amplitude, timing or the shape of the basic output pulse. The problem of code-dependent output impedance is discussed, including solutions. A state-of-the-art DAC design will be shown, including measurements and comparisons to theory and literature.

A comprehensive method for power estimation of residue amplifiers is presented. Using this method a definition of power efficiency is given, which subsequently is used to analyze recently published, highly efficient residue amplifiers. Design parameters are identified which have a key influence on the power efficiency and design choices based on power efficiency are discussed. It is shown that the most power efficient residue amplifier topologies share the same core circuit and differ primarily in how this core-circuit is driven from the input. Finally, an overview is given of these topologies, ranked on power efficiency.

Instrumentation applications, such as transducer readouts and smart sensors, require precision analog-to-digital converters (ADCs) with high absolute accuracy and linearity as well as high resolution. Such ADCs often result in poor energy-efficiency and high power consumption, thus making them unsuitable for the use in battery-powered autonomous systems. In this tutorial, it covers the design of energy-efficient high-resolution ADCs for sensor interfaces, which include both architectural- and circuit- level techniques to maintain the energy-efficiency. It also describes practical design aspects from several design examples.

The continuous feature size scaling in CMOS technology has enabled the system to decrease power consumption and lower costs while increasing reliability. The design of low-voltage opamp often poses significant challenges in the scaled CMOS technology. Dynamic amplifiers based on CMOS inverters attracts again and have become a necessity to minimize power consumption in all analog circuit blocks. This tutorial covers the design of energy-efficient inverter-based amplifiers, which includes recent advances to maintain the performance of analog circuitry. It also presents design examples of some state-of-the-art inverter-based amplifiers. 

This talk will discuss the most advanced techniques to achieve high spectral purity and low spur content in digital PLLs. Spur generation induced by nonlinear phase detection will be reviewed, as well as techniques aiming to mitigate nonlinearity of time-to-digital converters. The extension of digital bang-bang PLLs to fractional-N synthesis via the introduction of a digital-to-time converter and its linearity improvement techniques will be reviewed and analyzed.

This tutorial will introduce the fundamentals of analysis and practical implementation of digital PLLs. Unlike analog loops, the design of digital PLLs should take into account quantization, which can potentially generate limit cycles and degrade the output spectrum. A full design flow to meet bandwidth and jitter specifications, avoiding limit cycles, will be illustrated, and a comparison between digital PLLs based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors, will be shown.

Injection-locked phase-locked loops and multiplying delay-locked loops are the two main architectures of frequency synthesisers relaxing the trade-off between jitter and power consumption. This tutorial will first discuss jitter accumulation in realigned oscillators, from a theoretical point of view, and then show how lock range and output spectrum of realigned oscillators are linked to the so-called phase response curve. Finally, the realignment techniques will be extended to the case of fractional-N frequency synthesis and a practical design example of fractional-N multiplying DLL in CMOS will be illustrated.

A phase locked loop can enable the direct frequency- or phase-modulation of the carrier from a digital word, in a variety of different contexts, from polar RF transmitters to chirp generators for FMCW radars. This talk will review the main architectures allowing for wideband FM modulation and tight linearity, such as the two-point injection technique and the digital pre-distortion of the oscillator. Finally, the practical CMOS implementations of a 3.6-GHz phase modulator capable of GMSK/QPSK modulations, and a 20-GHz chirp generator for radar applications will be illustrated.

This talk introduces recent advancement of CMOS image sensors for biomedical applications. The fundamental operation principle is mentioned and then some recent topics on high performance characteristics are presented in terms of biomedical applications. Finally, biomedical applications with CMOS image sensor technology are demonstrated such as retinal prosthesis, fluorescence detection for ELISA, and implantable micro imaging devices.

Recently, combination of genetic engineering and optical technology enables to measure and control biological functions with light. Fluorescent protein such as GFP can be used as an optical tag of a specific molecule, and photoactive protein such as ChR2 can be applied for optical manipulation of biological functions.

This presentation introduces some kinds of implantable optical devices for measuring and controlling biological functions in the brain of a freely-moving rodent. Future direction is addressed for achieving bidirectional optical communication with brain.

Retinal prosthesis is a medical device that can partially restore visual sensation. In this talk, general introduction and present status of retinal prosthesis are presented. Then, issues to achieve a large number of stimulus electrodes are discussed in terms of circuit technology. 

Implantable medical devices (IMD) are nowadays widely employed to restore functions to the impaired individuals suffering from diseases like deafness, blindness, cardiac insufficiency,  incontinence, neural disorders, and many more. Such implantable systems become increasingly challenging, if a large number of sensing or stimulating sites needs to be realized - space and power budget, safety issues, high bidirectional data rates, as well as the vast number of electrical interfaces make the electronic circuit design a complex task of research and development.

This talk will highlight some of the recent worldwide advances towards the realization of high channel count implantable neural interfaces, covering applications and system examples such as the retinal implant and neural modulators with high efficiency frontends, as well as give an overview of the supporting circuitry, such as transcutaneous data telemetry including safety and security aspects, power telemetry, and adaptive power management. 

Continuous-time sigma-delta ADCs have obtained a dominant position for the digitization in wireless receivers. With steadily improved theoretical understanding, architectural innovations and excellent circuit designs, they have achieved bandwidths in the range of hundreds of MHz, while showing high resolution with unbeaten power efficiency. But there is more to it: continuous-time sigma-delta ADCs feature an implicit filtering, which becomes very attractive in the case of blocker or interferer scenarios, which is the usual case in wireless receivers. More recently, there have been a number of architectural and circuit innovations, which improved the robustness of the continuous-time sigma-delta ADC to such interferers, which are known as filtering ADCs. This talk covers different aspects of such continuous-time Σ∆ modulators: 

• Basic Operation and Architectures


• Influence of non-idealities and correction techniques


• Implicit anti-aliasing and signal-filtering


• Robustness to interferers- The filtering ADC


• State of the art Implementations

Power and data telemetry are mandatory components for all implantable systems. Especially multichannel recorders and stimulators require both large power and high data rates. Nonetheless, in many systems the telemetry is just implemented with a holistic approach, but not analyzed in large detail. Based on the fact that most implantable devices dissipate the largest amount of power in the telemetry subsystem, a careful design or even active adapt- ability of the link are thought necessary in order to provide high energy-efficiency as well as to meet with regulatory compliance. Still today, most systems use RF data telemetry and suffer from large power consumption. Power delivery is mostly done without feedback con- trol, or batteries are employed. On the emerging side, power efficient data transfer using UWB or non-RF telemetry, such as optical or ultrasonic approaches have shown to be excellent al- ternatives. Feedback controlled power telemetry or energy harvesting systems have shown high efficiency. This tutorial will give an overview and design guidelines for high-efficiency data and power telemetry for implantable systems. It first reviews the common RF based ap- proaches, and secondly highlights new approaches such as energy harvesting and non-RF communication.

Analog-digital converters are a dominant centerpiece of the digital revolution. Ever higher sampling frequencies and resolutions have to be achieved with increasingly better efficiency, thus lower power and area consumption. In this talk, the achievements in ADC designs over the last decades are shortly reviewed with a focus on what drove those advances, and what boundaries might impact future improvements. This is followed by a closer look to the frontline of the state-of-the-art, where the most recent circuit and system designs for SAR, sigma-delta, pipeline and hybrid ADCs are reviewed and explained.

Wideband millimeter-wave applications including wireless backhaul, WLAN, 5G cellular communication, and radar sensors require wide-tuning, fine-resolution frequency synthesizers with low phase noise and spurs. Although fractional-N digital PLL’s (DPLL) have been demonstrated to be advantageous over their analog counterparts at low GHz frequencies, analog PLL’s currently are predominant at millimeter-wave. Millimeter-wave DPLL’s are rare due to unsolved challenges in the digital phase extraction path that limit the achievable resolution, linearity, power consumption, and operating frequency.

In this talk, we will describe recent advances in the design of millimeter-wave DPLL's and their constituent blocks including inductor-less dividers, high-frequency time-to-digital converters, fine-resolution digitally controlled oscillators etc. We will also describe the extensive use of digital assistance schemes used in these blocks and also at the ADPLL subsystem level that are necessary to meet performance targets reliably in the face of PVT variations and mismatches.

Directional communication using antenna arrays will be a centerpiece of future communication systems in the sub-6 GHz bands and in the millimeter-wave bands. Currently, highly integrated phased-array transceivers are emerging that support steering the main lobe of the antenna array pattern, thereby improving the link budget and providing some spatial filtering. However, in order to increase data rates, network capacity and achieve better interference management, advanced multi-antenna techniques are deemed essential in future wireless networks. These techniques include various forms of multiple-input-multiple-output (MIMO) signaling, adaptive null-steering, spatial equalization, interference mitigation etc. This talk will present recent advances in the design of advanced beamforming transceivers that can support such multi-antenna signal processing. In particular, the design of phased arrays that can address very wide swaths of millimeter-wave spectrum, and the design of hybrid beamformers that can support millimeter-wave MIMO communication will be described.

With the burgeoning number of wireless standards occupying increasingly scarce spectrum, there is an urgent need to develop agile, wideband, interference-robust transceivers. The long-sought goal of such a “universally software reconfigurable” radio remains unfulfilled due to the lack of a CMOS-compatible RF switch of sufficiently high quality. Recently, a new class of reconfigurable RF circuits has emerged based on a new CMOS-compatible RF switch that uses “phase-change (PC)” materials. These materials can be reversibly transformed between low and high resistance states, have low parasitic capacitance. PC-based RF switches can therefore serve as a “more-than-Moore” element that can augment the capabilities of standard CMOS since they can be fabricated in the back-end of line of such technologies.

This talk describes recent advances in RF circuit reconfiguration using PC switches. A background into material choices and switch design considerations is provided, and is followed by a description of the design, fabrication and characterization of several CMOS+PC demonstration circuits that showcase this approach for RF reconfiguration. 

Smart sensors are complex systems comprising a sensor and its interface electronics, used to measure a physical parameter, such as temperature, humidity, pressure, acceleration,…, and converting the reading into the digital domain. Although often neglected, a reference is always required for any measurements, since measuring basically involves comparing the physical parameter of interest to a known quantity. Consequently, references are a fundamental components in any smart sensor, which can even limit the performance of the whole system if not properly designed. In this lecture, an overview of references for smart sensors will be given with specific focus on references that can be implemented on chip in a standard CMOS process. An overview of references available in CMOS will be presented, including resistance, capacitive, voltage, current and frequency references. We will discuss the need for references in smart sensors and their requirements, and explore through practical examples and case studies how the performance of integrated references can meet those requirements .

Nodes for the Internet-of-Things (IoT) need radios that are small, cheap and energy efficient. Frequency references are required for those radios to select the right band for wireless communication. Moreover, a frequency reference enables time synchronization between the nodes in the IoT network, which allows to turn off the radio when transmission or reception are not expected, thus resulting in power saving. Highly accurate frequency references can be implemented using quartz crystals but since such external components would limit the miniaturization of IoT nodes, fully integrated alternatives must be adopted. In addition, such references must guarantee the required accuracy over the wide temperature range expected in several IoT applications and over the supply voltage variations caused by the energy scavengers or the batteries powering the IoT node.

This talk will present the requirements for such fully integrated frequency references and review several alternatives for their implementation. The main sources of inaccuracy and the techniques to minimize their effect will be analyzed, with particular emphasis on supply sensitivity and temperature compensation.

Quantum computers hold the promise to change our everyday lives in this century in the same radical way as the classical computer did in the last century, by efficiently solving problems that are intractable today, such as large number factorization and simulation of quantum systems. Quantum processors must be cooled at cryogenic temperatures well below 1 K and each of their quantum bits (qubit) must be controlled by a classical electronic interface. Since future quantum processors with practical applications will require up to thousands or millions of quantum bits (qubit), the electronic controller must operate at cryogen­ic temperatures as close as possible to the quantum processor, to avoid the unpractical requirement of thousands of cables from the cryogenic refrigerator to a room-temperature controller. This talk will address how standard CMOS technology can be used to build such cryogenic electronic controller.
A brief introduction to quantum computers and their operation will be given, followed by a description of their hardware implementation and their requirements in terms of electronic control and read-out. We will address the challenges of building a scalable silicon-based cryogenic electronic controller, focusing on to use standard CMOS technology to build complex analog, mixed-signal and digital systems and circuits operating down to 4 K and below.

Jitter refers to deviation from ideal timing in clock and data transitions. In wireline communications, jitter reduces the timing margin available for clock and data recovery (CDR) circuits and poses significant challenges to signal integrity as the data rates march towards 64Gb/s/lane and beyond. In this talk, we first review the basic definitions of jitter and its properties, and the effects of jitter on CDR and other building blocks of a wireline system. We then describe the methods of characterizing, modeling, and simulating jitter. Finally, we present some recent works on jitter measurement and jitter mitigation techniques that are used to optimize the link performance.

This talk includes a selection of topics from Circuit Intuitions articles as the have appeared in the SSCS Magazine. The main audience for this talk would be upper-year undergraduate students but may also serve the interest of graduate students and practicing engineers. SSCS Chapter Chairs may request a select subset of Circuit Intuitions articles to be included in this talk.

There have been constant efforts to develop digital-intensive implementation of analog building blocks. The phase-locked loop (PLL), as a key analog block, has been one of the most actively researched topics in this area. The time-to-digital converter (TDC) plays a major role in determination of the achievable performance of digital PLL, and the requirements on TDC becomes even worse in fractional-N PLL. This presentation reviews principles of digital PLL with noise and jitter analyses. The talk also introduces implementation examples of recently proposed synthesizable fractional-N PLLs.

The on-chip oscillator has been widely adopted as a low-cost generator of timing reference for overall system. The requirements of the oscillators have been in the frequency stability, phase noise and power consumption. This presentation reviews basics of RC oscillator and introduces various approaches to overcome trade-off limitation between power consumption and immunity to process, supply, and temperature variations.

With the emergence of wearable and implantable technologies, there has been strong demand on the development of circuit techniques for ultra-low-power consumption while keeping traditional requirements of stable performance. The reference generator is an essential circuit block for supplying internal biases. This talk presents principles and issues in the design of nano-watt and sub-nano-watt implementations of CMOS and bandgap reference generators.

With many chip designs becoming more complex, and with time-to-market a key differentiation, leveraging IP is one compelling approach for chip development teams to gain a competitive edge. However, analog IP re-use has lagged behind digital IP due to challenges in customization, integration, and verification. The complex organizational relationships both within a company and between companies further complicate the IP ecosystem. This talk presents a high-level view of analog IP development and re-use, and uses conceived examples to illustrate some of the benefits and pitfalls of analog IP while gently challenging traditional notions of what it means to be an analog IC designer.

Compared to circuits utilizing voltage or current to convey analog signals, time-based circuits offer unique attributes, ranging from simple, area efficient quantization to more complex techniques for time-based processing such as integration, interpolation, and noise shaping. Although time-based circuits are not new, the availability of fast, low-power transistors in advanced process nodes, combined with the challenges of traditional analog design techniques, has renewed interest in time as a signal domain both in academia and in industry. This talk will look at some obvious and more subtle differences between voltage and time-based circuits, and discuss tradeoffs in the context of application requirements. A few advanced state-of-the-art time-based circuits will motivate the audience to consider how time-based circuits can be a useful tool for their own designs.

Time-based circuits have seen an increased use in advanced process nodes with fast transistors and low supply voltages. Specifically, high-performance ADC see benefits using time-based circuits due to the ease of quantizing binary time-based signals with simple digital circuits. This talk will discuss concepts such as phase-domain signals, noise-shaping, and metastability of time-based quantizers, highlighting a number of ADC architectures that directly utilize time. Finally, recent examples of state-of-the art time-based ADC will be reviewed.
 

This talk will describe methods to enable energy-efficient processing for deep learning, specifically convolutional neural networks (CNN), which is the cornerstone of many deep-learning algorithms. Deep learning plays a critical role in extracting meaningful information out of the zetabytes of sensor data collected every day. For some applications, the goal is to analyze and understand the data to identify trends (e.g., surveillance, portable/wearable electronics); in other applications, the goal is to take immediate action based the data (e.g., robotics/drones, self-driving cars, smart Internet of Things). For many of these applications, local embedded processing near the sensor is preferred over the cloud due to privacy or latency concerns, or limitations in the communication bandwidth. However, at the sensor there are often stringent constraints on energy consumption and cost in addition to throughput and accuracy requirements. Furthermore, flexibility is often required such that the processing can be adapted for different applications or environments (e.g., update the weights and model in the classifier). We will give a short overview of the key concepts in CNNs, discuss its challenges particularly in the embedded space, and highlight various opportunities that can help to address these challenges at various levels of design ranging from architecture, implementation-friendly algorithms, and advanced technologies (including memories and sensors).

Edge computing near the sensor is preferred over the cloud due to privacy or latency concerns for a wide range of applications including robotics/drones, self-driving cars, smart Internet of Things, and portable/wearable electronics.  However, at the sensor there are often stringent constraints on energy consumption and cost in addition to throughput and accuracy requirements. In this talk, we will describe how joint algorithm and hardware design can be used to reduce energy consumption while delivering real-time and robust performance for applications including deep learning, computer vision, autonomous navigation and video/image processing.  We will show how energy-efficient techniques that exploit correlation and sparsity to reduce compute, data movement and storage costs can be applied to various AI tasks including object detection, image classification, depth estimation, super-resolution, localization and mapping.  

Nowadays, the hearing aid technology is facing a new horizon based on advanced digital signal processing, wireless communication and artificial intelligence. In this lecture, new methodology with a systematic solution covering both the auditory periphery and the cognitive system is given. The up to date and rapidly evolves technologies for the binaural hearing aid system are well addressed. The multi-channel wide dynamic range compression, active noise reduction, self-adaptable directivity, acoustic scene analysis, and the wireless linking with other audio or communication systems are presented. The key technologies including the ultra-low power chip design, the advanced digital signal processing (DSP), and the wireless system integration and connectivity are discussed. The micromechanics and high performance electro-acoustics, the miniaturized antenna, the user interface, and the fitting system development are also the important aspects for the hearing aid technologies are shown in this lecture. A smart binaural hearing aid technology, which simultaneously processes the acoustic signals from the four microphones in both ears are indicated which utilizing the computing power from the smart phone to finish the advanced binaural DSP algorithms.

The demand of medical electronic devices, to make the medical devices smaller and smarter, is one of the driving force of integrated circuits and systems. The implantable medical devices (IMD’s), which are fully or partially implanted in the human bodies through surgeries, have a series of strict technical requirements including the choice of frequency and bandwidth, low power consumption, data rate, signal modulation method, disturbing and interference etc. This lecture focuses on a recently proposed technique in the art of radio transceiver design to reduce  power consumption and area occupation. A set of miniature IMD’s have been implemented using this ultra-low power transceiver which can be integrated in different application specific systems-on-a-chip (SoC’s).

To implant electronic systems into the human body  to perform sensing or stimulation in a minimally invasive manner has led to numerous medical advances. Progress in semiconductor technology has paved the way for making the implantable devices increasingly smarter and smaller, but the miniaturization of the power supply remains challenging. In order to power miniaturized implantable medical devices, wireless power transfer (WPT) is desirable. In the WPT system, improving the energy efficiency is a very important objective. The energy transfer efficiency should be as high as possible even with large variations of the coupling and loading conditions. In this lecture, the critical techniques for energy efficiency improvement are addressed. The methodologies include tracking the maximum efficiency point with a low-cost method, optimizing the efficiency of rectifiers and inverters, implementing the power control loop between the transceiver and receiver, increasing the quality factor (Q) of loop antenna coils and the coupling coefficient (k) between coils, and so on. Some systems level implementations of the WPT for popular bio-medical applications, such as involve Gastric Electric Stimulator (GES), Hearing Aid System, and digestive Tract Endoscopy System, are also presented in the lecture. A variety of special issues for these implementations have been discussed.

With 5G communication just around the corner, there is a rapidly increasing need for high-performance mm-Wave power amplifiers. However, these next-generation mm-Wave PAs are often expected to deliver nearly “perfect” performance. They should offer large output power to ensure sufficient link budget, broad bandwidth to support multi-standard communication or frequency reconfigurability/agility, high peak and back-off efficiency for energy saving, and also inherent linearity for Gbit/s complex modulations with minimum or even no digital pre-distortions (DPD). It is noteworthy that in conventional design notions a given PA design should typically take trade-offs among these performance aspects, instead of trying to achieve all of them. Interestingly, this somehow unreasonable quest for “perfect” mm-Wave PAs has recently stimulated a new wave of mm-Wave PA innovations at both circuit levels and architecture levels, which have substantially advanced the state of the art.

In this talk, we will review several recent mm-Wave PA designs that feature various design techniques and innovations at both circuit-level (nonlinearity compensation, continuous-mode operations, broadband harmonic tuning) and architecture-level (such as Doherty and outphasing PAs). We will also showcase several mm-Wave PA/antenna co-design examples that exploit new antenna structures as a new design paradigm to further enhance mm-Wave PA output power and efficiency.

Conventionally, antennas and electronic designs are often treated as two distinct and separated domains: antenna designers handle the antennas; circuit designers deal with the electronics; and they only talk to each other over one single standard 50ohm interface. It is noteworthy that the far-field antenna radiation characteristics are completely governed by its local current and voltage distributions, suggesting the possibility of using “multiple distributed electronics feeds” to “actively synthesize” desired antenna responses and achieve “element-level antenna reconfigurability.” The multi-feed antenna also can be viewed as a group of electrically small radiators, and the multiple feeds actively couple them together for collective high-performance radiation. Moreover, since on-chip antennas have become ubiquitous at mm-Wave and cost of adding more on-chip circuits are negligible, boundaries of these two domains are further blurred, and thus multi-feed antennas co-integrated with complex electronics now emerge as a very promising technology choice particularly for future mm-Wave massive MIMO systems.

In this talk, we will present several recently reported multi-feed radiators co-integrated with complex transmitter/receiver electronics in silicon to achieve unprecedented mm-Wave front-end performance. On-chip or on-package multi-feed antennas can support low-loss on-antenna power combining and radiation impedance down-scaling in one single antenna footprint, radically pushing the limit of output power and efficiency for mm-Wave transmitters in silicon. The multi-feed antennas also enable on-antenna active load modulation, achieving high-efficiency on-antenna Doherty or Outphasing silicon-based transmitters with state-of-the-art energy efficiency. Furthermore, inherently wideband feed isolation can be explored in multi-feed antennas to realize world-first mm-Wave full-duplex chip-to-chip communication link with Gbit/s 64QAM signals.

Living cells are highly complex systems that often exhibit multi-physics responses under external stimulus. Holistic cellular characterizations necessitates interface technologies that offer (1) single-cell resolution, (2) multi-modality interfacing with cells, (3) real-time two-way communication (sensing and actuation), (4) compatibility with high throughput massively parallel operations, and (5) possibility of production at commercial quantities. The nanometer-scale complementary metal-oxide semiconductor (CMOS) process is a potential candidate to realize cell-microelectronics interfaces. Electronics-based computations and signal processing, such as machine learning methods, may drastically relax the requirement on the physical interface and lead to further pixel miniaturization.

In this talk, we will present several fully integrated multi-modality CMOS cellular joint sensor/actuator arrays with multiple sensing modalities in every array pixel to characterize different cell physiological responses, including extracellular voltage recording, cellular impedance mapping, and optical detection with shadow imaging and bioluminescence sensing. Each pixel also contains electrical voltage/current excitation for cellular stimulation. These reported CMOS cellular joint sensor/actuator arrays comprise up-to 22k multi-modality pixels on each chip with spatial resolution down to 17um*17um/pixel, achieving single-cell resolution. Multi-modality cellular sensing at the pixel level is supported to enable holistic characterization and concurrent joint-modality physiological monitoring on the same cellular sample. Comprehensive biological experiments with different living cell samples demonstrate the screening functionalities.