Distinguished Lecturer Roster

"Everyone has been impressed by the vibrant and informative presentations of these renowned distinguished lecturers and valued the unique opportunity of having intimate technical discussions and exchanging ideas with such internationally recognized experts."

- Shahriar Mirabbasi, Chapter Chair of Vancouver SSCS, CPMT, and CESOC Joint Chapter, May 2015.

Terms through 31 December 2024

Fatih  Hamzaoglu portrait
Fatih Hamzaoglu
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Terms through 31 December 2024
Intel Fellow Director of New Memory Technologies

Fatih Hamzaoglu (SM’11) received his Ph.D. degree from the University of Virginia, Charlottesville, in 2002, in Electrical Engineering. After finishing the Ph.D., he joined Technology Development group at Intel Corporation, and since then, he has been working on memory technology developments such as SRAM, eDRAM, MRAM and RRAM. Currently, he’s an Intel Fellow and Director of New In-Package Memory Technologies, IP Design and Product Integration.

He is the author or coauthor of more than 40 papers and inventor/co-inventor of more than 30 patents. Dr. Hamzaoglu served in both VLSI Symposium Circuits Committee and ISSCC Memory Subcommittee between 2013 and 2019.

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PresentationAbstract
Journey through the Memory Tunnel: SRAM, (e)DRAM, MRAM and RRAM Array Designs and Applications Read Abstract
Firooz Aflatouni portrait
Firooz Aflatouni
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Terms through 31 December 2024
Department of Electrical and Systems Engineering, Associate Professor

Firooz Aflatouni (Senior Member, IEEE) received the Ph.D. degree in electrical engineering from the University of Southern California, Los Angeles, CA, USA, in 2011. In 1999, he co-founded Pardis Bargh Company, where he served as the CTO for five years working on the design and manufacturing of inclined-orbit satellite tracking systems. From 2004 to 2006, he was a Design Engineer with MediaWorks Integrated Circuits Inc., Irvine, CA. He was a Post-Doctoral Scholar with the Department of Electrical Engineering, California Institute of Technology, Pasadena, CA. He joined the University of Pennsylvania, Philadelphia, PA, USA, in 2014, where he is currently an Associate Professor with the Department of Electrical and Systems Engineering. His research interests include electronic–photonic co-design and low-power RF and millimeter-wave integrated circuits. Dr. Aflatouni received the 2020 Bell Labs Prize, the Young Investigator Program (YIP) Award from the Office of Naval Research in 2019, the NASA Early Stage Innovation Award in 2019, and the 2015 IEEE Benjamin Franklin Key Award. He is a Distinguished Lecturer of the Solid-State Circuit Society and has served on several IEEE program committees (ISSCC, CICC, and IMS). He is an Associate Editor of the IEEE Open Journal of the Solid-State Circuits Society and currently serves as the chair of IEEE Solid State Circuits Society (SSCS) Philadelphia chapter.

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PresentationAbstract
Electronic-photonic co-design; from imaging to optical phase control Read Abstract
Integrated photonic deep networks for image classification Read Abstract
Sudipto Chakraborty portrait
Sudipto Chakraborty
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Terms through 31 December 2024
IBM Research, Research Staff Member

Sudipto Chakraborty received his B. Tech from Indian Institute of Technology, Kharagpur in 1998 and Ph.D in EE from Georgia Institute of Technology in 2002. He worked as a researcher in Georgia Electronic Design Center (GEDC) till 2004. Since 2004 to 2016, he was a senior member of technical staff at Texas Instruments where he contributed to low power integrated circuit design in more than 10 product families in the areas of automotive, wireless, medical and microcontrollers. Since 2017, he has been working at the IBM T. J. Watson Research Center where he leads the low power circuit design for next generation quantum computing applications using nano CMOS technology nodes. He has authored or co-authored more than 75 papers, two books and holds 76 US patents. He has served in the technical program committees of various conferences including CICC, RFIC, IMS and has been elected as an IBM master inventor in 2022 for his contributions.

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PresentationAbstract
Current mode design techniques for low power transceivers Read Abstract
Low power cryo-CMOS design for quantum computing applications Read Abstract
Masum Hossain portrait
Masum Hossain
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Terms through 31 December 2024
Associate Professor, University of Alberta

Masum Hossain (M’11) received the B.Sc. degree from the Bangladesh University of Engineering and Technology, Dhaka, Bangladesh, in 2002, the M.Sc. degree from Queen’s University, Kingston, ON, Canada, in 2005, and the Ph.D. degree from the University of Toronto, Toronto, ON, in 2010. From 2007 to 2013, he worked in product development and industrial research, focusing on high-speed link design in multiple organizations, including Gennum and Rambus. In 2013, he joined the Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada. Recently in 2023, he joined Carleton University in Ottawa, Canada. Dr. Hossain received the Best Student Paper Award at the 2008 IEEE Custom Integrated Circuits Conference and the Analog Device’s Outstanding Student Designer Award in 2010. In 2021 he received EPS society nominated best paper award in IEEE Transaction in Components, Packaging and Manufacturing.

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PresentationAbstract
Digital equalization for Multilevel signaling in high-speed SerDes Read Abstract
Evolution of the Timing Recovery techniques in High-speed Links Read Abstract
Low-jitter flexible frequency generation for next-generation communication systems Read Abstract
Ping-Hsuan Hsieh portrait
Ping-Hsuan Hsieh
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Terms through 31 December 2024
Associate Professor at the Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan

Ping-Hsuan Hsieh received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Los Angeles, Los Angeles, CA, in 2004 and 2009, respectively. From 2009 to 2011, she was with the IBM T.J. Watson Research Center, Yorktown Heights, NY. In 2011 she joined the Electrical Engineering Department of National Tsing Hua University, Hsinchu, Taiwan, where she is currently an Associate Professor. Her research interests focus on mixed-signal integrated circuit designs for high-speed electrical data communications, clocking and synchronization systems, and energy-harvesting systems.

Prof. Hsieh served in the Technical Program Committee of the IEEE International Solid-State Circuits Conference, and is currently a member of the Technical Program Committees of the IEEE Asian Solid-State Circuits Conference and the IEEE Custom Integrated Circuits Conference. She served as an Associate Editor for the IEEE Internet of Things Journal from 2014 to 2018, a Guest Editor for the IEEE Journal of Solid-State Circuits Special Issue in 2021, and is currently an Associate Editor for the IEEE Open Journal of Circuits and Systems and IEEE Solid-State Circuits Letters.

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PresentationAbstract
An Overview on Interface Circuits and MPPT for Piezoelectric Energy Harvesting Read Abstract
Digitally-Enhanced Clock Generation and Distribution Read Abstract
Dongsuk Jeon portrait
Dongsuk Jeon
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Terms through 31 December 2024
Seoul National University, Seoul, Korea/ Associate Professor

Dongsuk Jeon received a B.S. degree in electrical engineering from Seoul National University, Seoul, South Korea, in 2009 and a Ph.D. degree in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, in 2014. From 2014 to 2015, he was a Post-doctoral Associate with the Massachusetts Institute of Technology, Cambridge, MA, USA. He is currently an Associate Professor with the Graduate School of Convergence Science and Technology, Seoul National University. His current research interests include hardware-oriented machine learning algorithms, hardware accelerators, and low-power circuits.

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PresentationAbstract
Designing an optimal hardware solution for deep neural network training Read Abstract
When circuits meet machine learning: circuit-based machine learning acceleration and machine learning-based circuit design Read Abstract
Joo-Young Kim portrait
Joo-Young Kim
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Terms through 31 December 2024
Professor, School of Electrical Engineering, KAISR

Joo-Young Kim (Senior Member, IEEE) received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2005, 2007, and 2010, respectively.

He is currently an Assistant Professor with the School of Electrical Engineering, KAIST. He is also the Director of the AI Semiconductor Systems Research Center, KAIST. His research interests span various aspects of hardware design, including VLSI design, computer architecture, field-programmable gate array (FPGA), domain-specific accelerators, hardware/software co-design, and agile hardware development. Before joining KAIST, he was a Senior Hardware Engineering Lead at Microsoft Azure, Redmond, WA, USA, working on hardware acceleration for its hyper-scale big data analytics platform named Azure Data Lake. He was also one of the initial members of Catapult project at Microsoft Research, Redmond, where he deployed a fabric of field-programmable gate arrays (FPGAs) in datacenters to accelerate critical cloud services, such as machine learning, data storage, and networking.

Dr. Kim was a recipient of the 2016 IEEE Micro Top Picks Award, the 2014 IEEE Micro Top Picks Award, the 2010 DAC/ISSCC Student Design Contest Award, the 2008 DAC/ISSCC Student Design Contest Award, and the 2006 A-SSCC Student Design Contest Award. He has served as a Guest Editor for the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), a Guest Editor for the IEEE Journal of Solid-State Circuits (JSSC), and an Associate Editor for the IEEE Transactions on Circuits and Systems—I: Regular Papers (TCAS-I).

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PresentationAbstract
A Multi-Accelerator Appliance for Accelerating Inference of Hyperscale Transformer Models Read Abstract
Processing-in-Memory for AI: From Circuits to Systems Read Abstract
Andrea Mazzanti portrait
Andrea Mazzanti
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Terms through 31 December 2024
Professor of Electronics at Università di Pavia

Andrea Mazzanti (S’02–M’09–SM’13) received the Laurea and Ph.D. degrees in electrical engineering from the University of Modena and Reggio Emilia, Modena, Italy, in 2001 and 2005, respectively. During the summer of 2003, he was with Agere Systems, Allentown, PA as an Intern. From 2006 to 2009, he was Assistant Professor with the University of Modena and Reggio Emilia. In January 2010, he joined the University di Pavia where he is now Full Professor of electronics. He has authored over 150 technical papers. His main research interests cover device modeling and IC design for high-speed communications, RF and millimeter-wave systems. Dr. Mazzanti has been a member of the Technical Program Committee of the IEEE Custom Integrated Circuit Conference (CICC) from 2008 to 2014, IEEE European Solid State Circuits Conference (ESSCIRC) and IEEE International Solid State Circuits Conference (ISSCC) from 2014 to 2018. He has been Associate Editor for the Transactions on Circuits and Systems-I from 2012 to 2015 and Guest Editor for special issues of the Journal of Solid State Circuits dedicated to CICC 2013-14 and ESSCIRC-2015. Since 2017, he has been serving as an Associate Editor for the IEEE Solid-State Circuits Letters.

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PresentationAbstract
Breaking the Phase-Noise Barrier with Multi-Core and Series-Resonance Harmonic Oscillators in BiCMOS Technology Read Abstract
Sugako Otani portrait
Sugako Otani
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Terms through 31 December 2024
System and Processor Architect at Renesas Electronics Corporation

Sugako Otani is a system and processor architect at Renesas Electronics Corporation. Her current research focuses on application-specific architectures, ranging from IoT devices to automotive. She joined Mitsubishi Electric Corporation, Japan, in 1995 after receiving an M.S. in physics from Waseda University, Tokyo. She received a Ph.D. in Electrical Engineering and Computer Science from Kanazawa University in 2015. From 2005 to 2006, she was a Visiting Scholar at Stanford University. She is a committee member of ISSCC, VLSI Symposium, ESSCIRC, and Cool Chips. Since 2019, she has been a Visiting Associate Professor at Nagoya University, Japan.

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PresentationAbstract
Automotive System Design Read Abstract
Tim Piessens portrait
Tim Piessens
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Terms through 31 December 2024
CTO of ICsense

Tim Piessens received the M.Sc. and Ph.D. degrees in electrical engineering from the Katholieke Universiteit Leuven, Leuven, Belgium, in 1998 and 2003, respectively. During his Ph.D., he focused on a new type of power amplifier/line driver for xDSL applications. In 2004, he co-founded ICsense, where he is the CTO and is responsible for the technical content of projects in the medical, automotive and consumer fields.

His current research interests include analog sensor readouts, non-linear system design, power management, high-voltage design and low-power, low-noise analog front-end design.

From 2014 till 2021, he was a member of the IEEE International Solid-State Circuits Conference Technical Program Committee. He was a member of the ISSCC EU leadership, the ISSCC executive committee and the ISSCC vision committee from 2019 till 2021 and ITPC EU chair in 2021. From 2020 on, he is a member of the ESSDERC-ESSCIRC Steering Committee.

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PresentationAbstract
Challenges in Battery Monitoring Systems for Electrical Vehicles Read Abstract
Design of Fully Integrated Charge Pumps Read Abstract
Design of High Performance Readout Chains for MEMS Barometric Pressure Sensors Read Abstract
High Performance, Low Power 3D Magnetic Hall Sensor design and challenges Read Abstract
Mingoo Seok portrait
Mingoo Seok
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Terms through 31 December 2024
Associate Professor, Columbia University

Mingoo Seok is an associate professor of Electrical Engineering at Columbia University. He received his B.S. from Seoul National University, South Korea, in 2005, and his M.S. and Ph.D. degree from the University of Michigan in 2007 and 2011, respectively, all in electrical engineering. His research interests are various aspects of VLSI circuits and architecture, including ultra-low-power integrated systems, cognitive and machine-learning computing, an adaptive technique for the process, voltage, temperature variations, transistor wear-out, integrated power management circuits, event-driven controls, and hybrid continuous and discrete computing. He won the 2015 NSF CAREER award and the 2019 Qualcomm Faculty Award. He is the technical program committee member for multiple conferences, including IEEE International Solid-State Circuits Conference (ISSCC). In addition, He has been an IEEE SSCS Distinguished Lecturer for Feb/2023-Feb/2025 and an associate editor for IEEE Transactions on Circuits and Systems Part I (TCAS-I) (2014-2016), IEEE Transactions on VLSI Systems (TVLSI) (2015-present), IEEE Solid-State Circuits Letter (SSCL) (2017-2022), and as a guest associate editor for IEEE Journal of Solid-State Circuits (JSSC) (2019).

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PresentationAbstract
Review, Survey, and Benchmark of Recent Digital LDO Voltage Regulators Read Abstract
SRAM-based In-Memory Computing Hardware: Analog vs Digital and Macros to Microprocessors Read Abstract
Farhana Sheikh portrait
Farhana Sheikh
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Terms through 31 December 2024
Principal Engineer at Intel’s Programmable Solution Group’s CTO Team

Dr. Farhana Sheikh is a Principal Engineer at Intel’s Programmable Solutions Group.  She has over 15 years of experience in ASIC and DSP/communications research including adaptive DSP, crypto, graphics, quantum wireless control, and 5G+ wireless. Since joining PSG, after 10+ years in Intel Labs, Farhana’s research focuses on 2D and 3D chiplet + FPGA integration research, with a focus on 3D heterogeneous integration for next generation wireless and sensing applications. Farhana has published over 50 papers and filed 22 patents, has initiated the AIB-3D open-source specification for 3D chiplet heterogeneous integration.  Farhana was instrumental in enabling Intel 16 for Intel’s IDM2.0 and is the co-creator of Intel’s University Shuttle Program.  Outside of Intel she volunteers for IEEE Solid-State Circuits Society (SSCS) and is the SSCS Women in Circuits Committee Chair.  Farhana is a co-recipient of 2020, 2019, and 2012 IEEE ISSCC Outstanding Paper Awards. In 2021, Farhana was recognized for her mentorship work with students and faculty by the Semiconductor Research Corporation (SRC) that awarded her the 2021 Mahboob Khan Outstanding Industry Liaison Award. She is IEEE SSCS Member-at-Large for 2022-2024, and IEEE SSCS Distinguished Lecturer for 2023 and 2024.

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PresentationAbstract
FPGA-Chiplet Architectures and Circuits for 2.5D/3D 6G Intelligent Radios Read Abstract
Laying the Foundation for Intelligently Adaptive Radios Read Abstract
Alberto Valdes Garcia portrait
Alberto Valdes Garcia
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Terms through 31 December 2024
Principal Research Scientist/Manager, IBM Thomas J. Watson Research Center
Alberto Valdes-Garcia is currently a Principal Research Scientist and Manager of the RF Circuits and Systems Group at the IBM T. J. Watson Research Center. In his current role, he leads a multi-disciplinary team that investigates and develops technologies that bridge the gap between antennas and edge-compute-based AI, enabling new millimeter-wave systems and applications for imaging and communications. Dr. Valdes-Garcia received the Ph.D. degree in Electrical Engineering from Texas A&M University in 2006. He holds >130 issued US patents and has authored >100 peer-reviewed publications. Recent awards include the 2017 Lewis Winner Award for Outstanding Paper, presented by the IEEE International Solid-State Circuits Conference, and the 2017 IEEE Journal of Solid-State Circuits Best Paper Award. In 2013, he was selected by the National Academy of Engineering for its Frontiers of Engineering Symposium. He currently serves in the Inaugural Editorial Board of the IEEE Journal of Microwaves and was the Chair of the IEEE MTT-S Microwave and Millimeter-Wave Integrated Circuits Committee in 2020-2021. Dr. Valdes-Garcia is a Senior Member of IEEE, was inducted into the IBM Academy of Technology in 2015, and was recognized as an IBM Master Inventor in 2016, 2019, and 2022.
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PresentationAbstract
3D millimeter-wave imaging and sensing with Si-based phased arrays, edge computing, and AI Read Abstract
Packaging and module integration as a catalyst for innovation in Si-based millimeter-wave systems Read Abstract
Jeff Walling portrait
Jeff Walling
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Terms through 31 December 2024
Associate Professor, Virgina Tech

Dr. Walling received the B.S. degree from the University of South Florida, Tampa, in 2000, and the M.S. and Ph. D. degrees from the University of Washington, Seattle, in 2005 and 2008, respectively. He was employed at Motorola, Plantation, FL working in cellular handset development. He interned for Intel from 2006-2007, working on highly-digital transmitters and CMOS PAs and continued this research while a Postdoctoral Researcher at the University of Washington. He was an associate professor in the ECE department at University of Utah, Head of RF Transceivers in the Microelectronic Circuits Centre Ireland at the Tyndall National Institute in Ireland, a Principal Engineer in Qualcomm CR&D, and a Senior Principal Engineer at Skyworks Solutions, Inc. He is presently an Associate Professor in the Bradley ECE Department at Virginia Tech. His research focuses on solutions for the next generation of wireless communication.

Dr. Walling has authored ~90 journal articles and conference papers and holds four patents with three pending. He gave a Keynote address at IEEE ESSCIRC on Digital Power Amplifiers in 2019, he received the Outstanding Teaching Award at University of Utah in 2015, the HKN Award for Excellence in Teaching in 2012, Best Paper Award at Mobicom 2012, the Yang Award for outstanding graduate research from the EE Department at University of Washington in 2008, an Intel Predoctoral Fellowship in 2007-2008, and the Analog Devices Outstanding Student Designer Award in 2006.

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PresentationAbstract
CMOS Power Amplifiers and Transmitters: The Evolution from 'Digital-Friendly' RF to 'Digital' RF Not yet available.
Digitally Friendly Transmitters for Next Generation Communications Not yet available.
Mixed-Mode Transceivers in CMOS Not yet available.
Zhengya  Zhang portrait
Zhengya Zhang
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Terms through 31 December 2024
Associate Professor, University of Michigan, Ann Arbor

Zhengya Zhang received the B.A.Sc. degree from the University of Waterloo in Canada in 2003, and the M.S. and Ph.D. degrees from UC Berkeley in 2005 and 2009. He has been a faculty member at the University of Michigan, Ann Arbor since 2009. His research is in low-power and high-performance integrated circuits and systems for computing, communications, and signal processing. Dr. Zhang was a recipient of the NSF CAREER Award, the Intel Early Career Faculty Award, the Neil Van Eenam Memorial Award from the University of Michigan, and the David J. Sakrison Memorial Prize from UC Berkeley. He served on the program committees of the Symposia on VLSI Technology and Circuits and CICC, and the editorial board of the IEEE Transactions on VLSI Systems.

 

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PresentationAbstract
Machine Learning Hardware Design for Efficiency, Flexibility and Scalability Read Abstract
The Challenges and Opportunities in the Path Towards Chipletization Read Abstract

Terms through 31 December 2025

Keith Bowman portrait
Keith Bowman
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Terms through 31 December 2025
Qualcomm

Keith A. Bowman is a Principal Engineer and Manager in the System-on-Chip (SoC) Research Lab at Qualcomm Technologies, Inc. in Raleigh, NC, USA.  He directs the research and development of circuit and system technologies to improve the performance, energy efficiency, yield, reliability, and security of Qualcomm processors.  He pioneered the invention, design, and test of Qualcomm’s first commercially successful circuit for mitigating the adverse effects of supply voltage droops on processor performance, energy efficiency, and yield.  He received the B.S. degree from North Carolina State University in 1994 and the M.S. and Ph.D. degrees from the Georgia Institute of Technology in 1995 and 2001, respectively, all in electrical engineering.  From 2001 to 2013, he worked in the Technology Computer-Aided Design (CAD) Group and the Circuit Research Lab at Intel Corporation in Hillsboro, OR, USA.  In 2013, he joined the Qualcomm Corporate Research and Development (CRD) Processor Research Team.

 

Dr. Bowman has published 90+ technical papers in refereed conferences and journals, authored one book chapter, received 30+ US patents and 50+ international patents, and presented 50+ tutorials on variation-tolerant circuit designs.  He received the 2016 Qualcomm CRD Distinguished Contributor Award for Technical Contributions, representing CRD’s highest recognition, for the pioneering invention of the auto-calibrating adaptive clock distribution circuit, which significantly enhances processor performance, energy efficiency, and yield and is integral to the success of the Qualcomm® Snapdragon™ 820 and future processors.  He received the 2022 Qualcomm IP Achievement Award for high-quality inventions, leading to strong processor performance and energy-efficiency improvements and differentiated products.  Since 2018, he served on the Qualcomm Low-Power Circuit Design Patent Review Board.  In 2019 and 2020, he was as an IEEE SSCS Distinguished Lecturer (DL).  He is currently serving a 2nd 2-year term as an IEEE SSCS DL.  From 2020 to 2023, he served as an IEEE SSCS Mentor.  He was the International Technical Program Committee (ITPC) Chair and the General Conference Chair for ISQED in 2012 and 2013, respectively, and for ICICDT in 2014 and 2015, respectively.  He has served on the ISSCC ITPC as a member of the Digital Circuits (DCT) Subcommittee from 2016 to 2020 and as the DCT Chair from 2020 to 2024.  He currently serves as the ISSCC Program Vice Chair.  He is a Fellow of the IEEE.

Dr. Bowman has published over 80 technical papers in refereed conferences and journals, authored one book chapter, received 19 patents, and presented 38 tutorials on variation-tolerant circuit designs.  He received the 2016 Qualcomm Corporate Research and Development (CRD) Distinguished Contributor Award for Technical Contributions, representing CRD’s highest recognition, for the pioneering invention of the auto-calibrating adaptive clock distribution circuit, which significantly enhances processor performance, energy efficiency, and yield and is integral to the success of the Qualcomm® Snapdragon 820 and future processors.  He was the Technical Program Committee (TPC) Chair and the General Conference Chair for ISQED in 2012 and 2013, respectively, and for ICICDT in 2014 and 2015, respectively.  Since 2016, he has served on the ISSCC TPC.

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PresentationAbstract
Adaptive Processor Designs Read Abstract
Wei Deng portrait
Wei Deng
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Terms through 31 December 2025
Tsinghua University

Wei Deng received the B.S. and M.S. degrees from the University of Electronic Science and Technology of China (UESTC), China, in 2006 and 2009, respectively, and the Ph.D. degree from the Tokyo Institute of Technology, Japan, in 2013. He was with Apple Inc., Cupertino, CA, USA, working on RF, mm-wave, and mixed-signal IC design for wireless transceivers and Apple A-series processors. Currently he is with Tsinghua University, Beijing, China, as an Associate Professor. His research interests include RF, mm-wave, terahertz, and mixed-signal integrated circuits and systems for wireless communications and radars systems. He has authored or co-authored more than 160 IEEE journal and conference articles. Dr. Deng is a Technical Program Committee (TPC) Member of ISSCC, VLSI, A-SSCC, CICC and ESSCIRC. He has been an Associate Editor and a Guest Editor of the IEEE Solid-State Circuits Letters (SSC-L), and a Guest Editor of the IEEE Journal of Solid-state Circuits (JSSC).

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PresentationAbstract
High-Performance PLLs: Evolution, Challenges, and Future Directions Read Abstract
Joint Radar-communication CMOS Transceiver: From System Architecture to Circuit Design Read Abstract
Timothy (Tod) Dickson portrait
Timothy (Tod) Dickson
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Terms through 31 December 2025
IBM T.J. Watson Research Center

Timothy O. (Tod) Dickson received dual B.Sc. degrees in electrical and computer engineering with highest honors from the University of Florida in 1999.  He completed the M. Eng degree at the University of Florida in 2002 and the Ph.D. degree at the University of Toronto in 2006, both in electrical engineering.

His Ph.D. work was in the area of serial transceivers operating up to 80 Gb/s in SiGe BiCMOS technologies, focusing on the development of low-noise and low-power design methodologies.  In 2006, he joined the IBM T.J. Watson Research Center in Yorktown Heights, N.Y where he is currently a Principal Research Scientist.  His research focuses on the design of high-speed, low-power serial transceivers for electrical and optical links.  Since 2014, he has served on the Technical Advisory Board of the Semiconductor Research Corporation Analog-Mixed Signal Circuits, Systems, and Devices (AMS-CSD) thrust.  He is also an Adjunct Professor at Columbia University, where he has taught graduate level courses in analog and mixed-signal integrated circuit design since 2007.

Dr. Dickson has been a recipient or co-recipient of several best paper awards, including the Best Paper Award for the 2009 IEEE Journal of Solid-State Circuits, the Beatrice Winner Award for Editorial Excellence at the 2009 ISSCC, the Best Paper Award at the 2015 IEEE Custom Integrated Circuits Conference (CICC), and the Best Student Paper Award at the 2004 Symposium on VLSI Circuits  He was a member of the Technical Program Committee (TPC) of the IEEE Compound Semiconductor Integrated Circuit Symposium from 2007-2009, and of the IEEE CICC from 2017-2023 where he chaired the wireline subcommittee. He was a guest editor of the October 2010 issue of the IEEE Journal of Solid-State Circuits. From 2018-2023, he was an Associate Editor for the IEEE Solid-State Circuits Letters. Since 2024 he has been an Associate Editor for the IEEE Open Journal of the Solid-State Circuits Society. He is an IEEE Senior Member

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PresentationAbstract
High-Speed DACs for 100+ Gb/s Wireline Links Read Abstract
Makoto Ikeda portrait
Makoto Ikeda
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Terms through 31 December 2025
The University of Tokyo, Tokyo, Japan

Makoto Ikeda received the BE, ME, and Ph.D. degrees in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1991, 1993 and 1996, respectively. He joined the University of Tokyo as a research associate, in 1996, and now professor and director of Systems Design Lab(d.lab), the University of Tokyo. At the same time he has been involving the activities of VDEC(VLSI Design and Education Center, the University of Tokyo), to promote VLSI design educations and researches in Japanese academia. He worked for hardware security, asynchronous circuits design, smart image sensor for 3-D range finding, and time-domain signal processing. He has been serving various positions of various international conferences, including ISSCC ITPC Chair(ISSCC 2021), IMMD sub-committee chair (ISSCC 2015-2018), A-SSCC 2015 TPC Chair, VLSI Circuits Symposium PC Chair(2017)&Symposium Chair(2019). He is a senior member of IEEE, IEICE Japan, and a member of IPSJ and ACM.

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PresentationAbstract
Acceleration of Encryption Algorithms, Elliptic Curve, Pairing, Post Quantum Cryptoalgorithm (PQC), and Fully Homomorphic Encryption (FHE) Read Abstract
Basics of Asynchronous circuits design Read Abstract
Low-voltage design with autonomous control by gate-level hand-shaking Read Abstract
Taekwang Jang portrait
Taekwang Jang
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Terms through 31 December 2025
ETH Zürich

Taekwang Jang (S’06-M’13-SM’19) received his B.S. and M.S. in electrical engineering from KAIST, Korea, in 2006 and 2008, respectively. From 2008 to 2013, he worked at Samsung Electronics Company Ltd., Yongin, Korea, focusing on mixed-signal circuit design, including analog and all-digital phase-locked loops for communication systems and mobile processors. In 2017, he received his Ph.D. from the University of Michigan and worked as a post-doctoral research fellow at the same institution. In 2018, he joined ETH Zürich as an assistant professor and is leading the Energy-Efficient Circuits and Intelligent Systems group. He is also a member of the Competence Center for Rehabilitation Engineering and Science, and the chair of the IEEE Solid-State Circuits Society, Switzerland chapter. His research focuses on circuits and systems for highly energy-constrained applications such as wireless sensor nodes and biomedical interfaces. Essential building blocks such as a sensor interface, energy harvester, power converter, communication transceiver, frequency synthesizer, and data converters are his primary interests. He holds 15 patents and has (co)authored more than 80 peer-reviewed conferences and journal articles. He is the recipient of the 2024 IEEE Solid-State Circuits Society New Frontier Award, the SNSF Starting Grant, the IEEE ISSCC 2021 and 2022 Jan Van Vessem Award for Outstanding European Paper, the IEEE ISSCC 2022 Outstanding Forum Speaker Award, and the 2009 IEEE CAS Guillemin-Cauer Best Paper Award. Since 2022, he has been a TPC member of the IEEE International Solid-State Circuits Conference (ISSCC), IMMD Subcommittee, and IEEE Asian Solid-State Circuits Conference (ASSCC), Analog Subcommittee. He also chaired the 2022 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Frequency Generation Subcommittee. Since 2023, he has been serving as an Associate Editor for the Journal of Solid-State Circuits (JSSC) and was appointed as a Distinguished Lecturer for the Solid-State Circuits Society in 2024.

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PresentationAbstract
Energy-Efficient Sensor Interface Read Abstract
Fully integrated DC-DC Conversion Read Abstract
Low Power Frequency Generation Read Abstract
Hyun-Sik Kim portrait
Hyun-Sik Kim
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Terms through 31 December 2025
KAIST, Daejeon, Korea

Hyun-Sik Kim is currently an Associate Professor of Electrical Engineering at the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea. He received his B.S. degree (Hons.) in electronic engineering from Hanyang University, Seoul, South Korea, in 2009, and his M.S. and Ph.D. degrees in electrical engineering from KAIST, in 2011 and 2014, respectively. His research interests include the CMOS analog-integrated circuit designs, with an emphasis on display drivers, power managements, and sensory readout chips. Prof. Kim was a recipient of two Gold Prizes in the 18th and 19th Samsung Human-Tech Paper Awards in 2012 and 2013, respectively, the IEEE SSCS Pre-Doctoral Achievement Award in 2014, the IEEE SSCS Seoul Chapter Best Student JSSC Paper Award in 2014, and the KAIST Technology Innovation Award in 2022. He served as a guest editor of the IEEE Solid-State Circuits Letters (SSC-L) and is currently serving on the Technical Program Committees (TPC) for the IEEE International Solid-State Circuits Conference (ISSCC), the IEEE Asian Solid-State Circuits Conference (A-SSCC), and the IEEE Custom Integrated Circuits Conference (CICC).

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PresentationAbstract
Current-Shared Cluster of Multiple Integrated Voltage Regulators (IVRs) Read Abstract
Display Driver ICs – From Basics to Recent Design Challenges Read Abstract
Exploring Ways to Minimize Dropout Voltage for Energy-Efficient LDO Regulators Read Abstract
Rabia Kirby Yazicigil portrait
Rabia Kirby Yazicigil
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Terms through 31 December 2025
Boston University

Rabia Yazicigil is an Assistant Professor of ECE Department at Boston University and a Network Faculty at Sabanci University. She was a Postdoctoral Associate at MIT and received her Ph.D. degree from Columbia University in 2016. Her research interests lie at the interface of integrated circuits, bio-sensing, signal processing, security, and wireless communications to innovate system-level solutions for future energy-constrained applications. She has received numerous awards, including the NSF CAREER Award (2024), Early Career Excellence in Research Award for the Boston University College of Engineering (2024), the Catalyst Foundation Award (2021), Boston University ENG Dean Catalyst Award (2021), and “Electrical Engineering Collaborative Research Award” for her Ph.D. research (2016). Dr. Yazicigil is an active member of the Solid-State Circuits Society (SSCS) Women-in-Circuits committee and is a member of the 2015 MIT EECS Rising Stars cohort. She was recently selected as an IEEE SSCS Distinguished Lecturer and elected to the IEEE SSCS AdCom as a Member-at-Large. Lastly, she serves as an Associate Editor of the IEEE Transactions on Circuits and Systems-I (TCAS-I) and on the IEEE ISSCC, RFIC, ESSCIRC, and DAC Technical Program Committees.

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PresentationAbstract
All-In-One Data Decoders Using GRAND Read Abstract
Cyber-Secure Biological Systems (CSBS) Read Abstract
Physical-Layer Security for Latency- and Energy-Constrained Integrated Systems Read Abstract
Makoto Nagata portrait
Makoto Nagata
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Terms through 31 December 2025
Kobe University

Makoto Nagata (Senior Member, IEEE) received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, Japan, in 1991 and 1993, respectively, and the Ph.D. degree in electronics engineering from Hiroshima University, Hiroshima, Japan, in 2001.

He was a Research Associate at Hiroshima University from 1994 to 2002, an Associate Professor at Kobe University, Kobe, Japan, from 2002 to 2009, where he was promoted to a Full Professor in 2009.

His research interests include design techniques targeting high-performance mixed analog, RF and digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility, testing and diagnosis, 2.5D and 3D system integration, as well as their applications for hardware security and hardware safety, and cryogenic electronics for quantum computing.

Dr. Nagata is a Senior Member of IEICE. He has been a member of a variety of technical program committees of international conferences, such as the Symposium on VLSI Circuits (2002–2009), Custom Integrated Circuits Conference (2007–2009), Asian Solid-State Circuits Conference (2005–2009), International Solid-State Circuits Conference (2014-2022), European Solid- State Circuits Conference (since 2020), and many others. He chaired the Technology Directions subcommittee for International Solid-State Circuits Conference (2018-2022) and served for an Executive Committee Member (2023-present). He was the Technical Program Chair (2010–2011), the Symposium Chair (2012–2013), and an Executive Committee Member (2014–2015) for the Symposium on VLSI circuits. He was the IEEE Solid-State Circuits Society (SSCS) AdCom member (2020-2022), the distinguished lecturer (2020-2021, and 2024-present), and currently serves as the chapters vice chair (2022-) of the society. He is an associate editor for IEEE Transactions on VLSI Systems (since 2015).

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PresentationAbstract
Hardware Security and Safety of IC Chips and Systems Read Abstract
IC Chip and Packaging Interactions for Performance Improvements and Security Protections Read Abstract
RF Noise Coupling -- Understanding, Mitigation and Impacts on Wireless Communication Performance of IC Chips and Systems Read Abstract
Secure Packaging, Tamper Resistance, and Supply Chain Security of IC Chips Read Abstract
Maurits Ortmanns portrait
Maurits Ortmanns
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Terms through 31 December 2025
University of Ulm
Maurits Ortmanns (Senior Member, IEEE) received the degree of Dr.-Ing. from the University of Freiburg, Germany, in 2004. From 2004 to 2005, he worked at Sci-Worx GmbH, Hannover, Germany, in the area of mixed-signal circuits for biomedical implants. In 2006, he joined the University of Freiburg as an assistant professor. Since 2008, he is a full professor at the University of Ulm, Germany, where he is the director of the Institute of Microelectronics. He is the author of the textbook Continuous-Time Sigma-Delta A/D Conversion, author or co-author of several other book chapters, and over 350 IEEE journal articles and conference papers. He holds many patents. He has served as a program committee member of ISSCC, ESSCIRC, DATE, and ECCTD, as ISSCC EU regional chair, and ISSCC analog subcommittee chair. He has served as an Associate Editor for TCAS, Guest Editor for JSSC, and as a Distinguished Lecturer for SSCS. His research interests include mixed-signal integrated circuit design with special emphasis on data converters and biomedical applications.
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PresentationAbstract
Efficient High Resolution Incremental ADCs Read Abstract
Implantable Integrated Circuits and Systems for Neurostimulation and Neuromodulation Read Abstract
Shanthi Pavan portrait
Shanthi Pavan
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Terms through 31 December 2025
Indian Institute of Technology
Shanthi Pavan received the B.Tech. degree in electronics and communication engineering from IIT Madras, Chennai, India, in 1995, and the M.S. and D.Sc. degrees from Columbia University, New York, NY, USA, in 1997 and 1999, respectively. From 1997 to 2000, he was with Texas Instruments, Warren, NJ, USA, where he worked on high-speed analog filters and data converters. From 2000 to June 2002, he worked on microwave ICs for data communication at Bigbear Networks, Sunnyvale, CA, USA. Since July 2002, he has been with IIT Madras, where he is currently the NT Alexander Institute Chair Professor of Electrical Engineering.

Prof.Pavan is the author of Understanding Delta-Sigma Data Converters (second edition, with Richard Schreier and Gabor Temes), which received the Wiley-IEEE Press Professional Book Award for the year 2020. His research interests are in the areas of high-speed analog circuit design and signal processing. Dr. Pavan is a fellow of the Indian National Academy of Engineering, and the Indian National Science Academy, and the recipient of several awards, including the IEEE Circuits and Systems Society Darlington Best Paper Award in 2009. He has served as the Editor-in-Chief of the IEEE Transactions on Circuits and Systems—I: Regular Papers and on the Technical Program Committee of the International Solid-State Circuits Conference (ISSCC). He has served as a Distinguished Lecturer of the IEEE Circuits and Systems Society and is a two-term Distinguished Lecturer of the Solid-State Circuits Society. He currently serves as the Vice-President of Publications of the IEEE Solid-State Circuits Society and on the editorial board of the IEEE Journal of Solid-State Circuits. He is an IEEE Fellow.
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PresentationAbstract
Continuous-Time Pipelined Analog-to-Digital Converters - Where Filtering Meets Analog-to-Digital Conversion Read Abstract
Design Challenges in Precision Continuous-Time Delta Sigma Data Conversion Read Abstract
Shreyas Sen portrait
Shreyas Sen
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Terms through 31 December 2025
Weldon School of Biomedical Engineering, Purdue University
Shreyas Sen is an Elmore Associate Professor of ECE & BME, Purdue University. His current research interests span mixed-signal circuits/systems and electromagnetics for the Internet of Bodies (IoB) and Hardware Security. He has authored/co-authored 3 book chapters, over 200 journal and conference paper and has 25 patents granted/pending. Dr. Sen serves as the Director of the Center for Internet of Bodies (C-IoB) at Purdue. Dr. Sen is the inventor of the Electro-Quasistatic Human Body Communication (EQS-HBC), or Body as a Wire technology, for which, he is the recipient of the MIT Technology Review top-10 Indian Inventor Worldwide under 35 (MIT TR35 India) Award in 2018 and Georgia Tech 40 Under 40 Award in 2022. To commercialize this invention Dr. Sen founded Ixana and serves as the Chairman and CTO and led Ixana to awards such as 2x CES Innovation Award 2024, EE Times Silicon 100, Indiana Startup of the Year Mira Award 2023, among others. His work has been covered by 250+ news releases worldwide, invited appearance on TEDx Indianapolis, NASDAQ live Trade Talks at CES 2023, Indian National Television CNBC TV18 Young Turks Program, NPR subsidiary Lakeshore Public Radio and the CyberWire podcast. Dr. Sen is a recipient of the NSF CAREER Award 2020, AFOSR Young Investigator Award 2016, NSF CISE CRII Award 2017, Intel Outstanding Researcher Award 2020, Google Faculty Research Award 2017, Purdue CoE Early Career Research Award 2021, Intel Labs Quality Award 2012 for industrywide impact on USB-C type, Intel Ph.D. Fellowship 2010, IEEE Microwave Fellowship 2008, GSRC Margarida Jacome Best Research Award 2007, and nine best paper awards including IEEE CICC 2019, 2021 and in IEEE HOST 2017-2020, for four consecutive years. Dr. Sen's work was chosen as one of the top-10 papers in the Hardware Security field (TopPicks 2019). He serves/has served as an Associate Editor for IEEE Solid-State Circuits Letters (SSC-L), Nature Scientific Reports, Frontiers in Electronics, IEEE Design & Test, Executive Committee member of IEEE Central Indiana Section and Technical Program Committee member of TPC member of ISSCC, CICC, DAC, CCS, IMS, DATE, ISLPED, ICCAD, ITC, and VLSI Design. Dr. Sen is a Senior Member of IEEE.
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PresentationAbstract
Recent Circuit Advances for Resilience to Side-Channel Attacks Read Abstract
Secure and Efficient Internet of Bodies using Electro-Quasistatic Human Body Communication Read Abstract
Sai-Weng Sin portrait
Sai-Weng Sin
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Terms through 31 December 2025
Associate Professor, University of Macau

Sai-Weng Sin (Terry) (Senior Member, IEEE) received the B.S., M.S., and Ph.D. degrees in electrical and electronics engineering from the University of Macau, Macao, China, in 2001, 2003, and 2008, respectively. He is currently an Associate Professor in the Faculty of Science and Technology, University of Macau, and is the Deputy Director of State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China. He has published 1 book entitled “Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters” in Springer, holds 12 patents and over 170 technical journals and conference papers in the field of high-performance data converters and analog mixed-signal integrated circuits.

 

Dr. Sin currently serves as Student Demonstration Program Chair in the Technical Program Committee of the IEEE Asian Solid-State Circuits Conference (A-SSCC), subcommittee chair of the International Conference on Integrated Circuits, Technologies and Applications (ICTA). He served as a Review Committee Member of the International Symposium on Circuits and Systems (ISCAS). He is currently an Associate Editor-in-Chief (Digital Communications) of the IEEE Transaction on Circuits and Systems II – Express Briefs, and also the Associate Editors of IEEE Access and Journal of Semiconductors. He is an IEEE SSCS Distinguished Lecturer for 2024 and 2025. He was the co-recipient of the 2011 ISSCC Silk Road Award, Student Design Contest Award in A-SSCC 2011, and the 2011 State Science and Technology Progress Award (second-class), China.

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PresentationAbstract
The Historical Development of Data Converters – ADCs that last from 1954 to 2024 Read Abstract
Weightings in Incremental ADCs – How the weights can break and make the Incremental ADCs Read Abstract
Vivienne Sze portrait
Vivienne Sze
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Terms through 31 December 2025
Massachusetts Institute of Technology
Vivienne Sze is an Associate Professor in the Electrical Engineering and Computer Science Department at MIT. She works on computing systems that enable energy-efficient machine learning, computer vision, and video compression/processing for a wide range of applications, including autonomous navigation, digital health, and the internet of things. She is widely recognized for her leading work in these areas and has received awards, including faculty awards from Google, Facebook, and Qualcomm, the Symposium on VLSI Circuits Best Student Paper Award, the IEEE Custom Integrated Circuits Conference Outstanding Invited Paper Award, and the IEEE Micro Top Picks Award. As a member of the Joint Collaborative Team on Video Coding, she received the Primetime Engineering Emmy Award for the development of the High-Efficiency Video Coding video compression standard.  She is a co-editor of High Efficiency Video Coding (HEVC): Algorithms and Architectures (Springer, 2014) and co-author of Efficient Processing of Deep Neural Networks (Synthesis Lectures on Computer Architecture, Morgan Claypool, 2020). For more information about Prof. Sze’s research, please visit http://sze.mit.edu.
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PresentationAbstract
Efficient Computing for AI and Robotics: From Hardware Accelerators to Algorithm Design Read Abstract
Efficient Computing for Autonomy and Navigation Read Abstract
Jerald Yoo portrait
Jerald Yoo
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Terms through 31 December 2025
Seoul National University

Jerald Yoo (S’05-M’10-SM’15) received the B.S., M.S., and Ph.D. degrees in Department of Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2002, 2007, and 2010, respectively. 

From 2010 to 2016, he was with the Department of Electrical Engineering and Computer Science, Masdar Institute, Abu Dhabi, United Arab Emirates, where he was an Associate Professor. From 2010 to 2011, he was also with the Microsystems Technology Laboratories (MTL), Massachusetts Institute of Technology (MIT) as a visiting scholar. Between 2017 and 2024, he was with the Department of Electrical and Computer Engineering, National University of Singapore, Singapore, as an Associate Professor. Since 2024, he has been with the Department of Electrical and Computer Engineering, Seoul National University, where he is currently an Associate Professor. He has pioneered research on Body-Area Network (BAN) transceivers for communication/powering and wearable body sensor network using the planar-fashionable circuit board for a continuous health monitoring system. He authored book chapters in Biomedical CMOS ICs (Springer, 2010), Enabling the Internet of Things—From Circuits to Networks (Springer, 2017), The IoT Physical Layer (Chapter 8, Springer, 2019) and Handbook of Biochips (Biphasic Current Stimulator for Retinal Prosthesis, Springer, 2021). His current research interests include low-energy circuit technology for wearable bio-signal sensors, flexible circuit board platform, BAN for communication and powering, ASIC for piezoelectric Micromachined Ultrasonic Transducers (pMUT), and System-on-Chip (SoC) design to system realization for wearable healthcare applications.

Dr. Yoo is an IEEE Solid-State Circuits Society (SSCS) Distinguished Lecturer (2024-2025 and 2017-2018). He also served an IEEE Circuits and Systems Society (CASS) Distinguished Lecturer (2019-2021). He is the recipient or a co-recipient of several awards: IEEE International Solid-State Circuits Conference (ISSCC) 2020 and 2022 Demonstration Session Award (Certificate of Recognition), IEEE International Symposium on Circuits and Systems (ISCAS) 2015 Best Paper Award (BioCAS Track), ISCAS 2015 Runner-Up Best Student Paper Award, the Masdar Institute Best Research Award in 2015 and the IEEE Asian Solid-State Circuits Conference (A-SSCC) Outstanding Design Award (2005). He was the founding vice-chair of the IEEE SSCS United Arab Emirates (UAE) Chapter and is the chair of the IEEE SSCS Singapore Chapter. Currently, he serves as an Executive Committee as well as a Technical Program Committee Member of the IEEE International Solid-State Circuits Conference (ISSCC), ISSCC Student Research Preview (chair), and IEEE Asian Solid-State Circuits Conference (A-SSCC, Emerging Technologies, and Applications Subcommittee Chair), and Steering Committee Member of IEEE Transactions on Biomedical Circuits and Systems (TBioCAS). He is also an Analog Signal Processing Technical Committee Member of IEEE Circuits and Systems Society and was an Associate Editor of IEEE Transactions on Biomedical Circuits and Systems (TBioCAS) and IEEE Open Journal of Solid-State Circuits Society (OJ-SSCS). 

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PresentationAbstract
Body Area Network – Connecting and powering things together around the body Read Abstract
Low-power, Low-noise Sensor Interface Circuits for Biomedical Applications Read Abstract
On-Chip Epilepsy Detection: Where Machine Learning Meets Patient-Specific Wearable Healthcare Read Abstract
Towards Monolithic Mobile Ultrasound Imaging System for Medical and Drone Applications Read Abstract