“Interconnect Gap” has been a long-standing grand challenge caused by the gap between the ever-increasing data rate demand and the insufficient capabilities. The capacity challenge is further deteriorated with simultaneous challenges of energy efficiency and cost. Existing electrical interconnect (EI) and optical interconnect (OI) face fundamental difficulties to completely address the interconnect issues individually. THz Interconnect (TI), utilizing the frequency spectrum sandwiched between microwave and optical frequencies, holds the high potentials to complement EI and OI by leveraging the advantages of both electronics and optics. In this talk, I will present our research activities in the high potential TI field, including THz silicon waveguide channel development, TI system demonstration, dispersion constrained link bandwidth and mitigation schemes such as mode division and frequency division multiplexing based channelization.

3D stacking and backside illuminated (BSI) CMOS image sensor (CIS) manufacturing technologies offer a means to unleash the full potential of single photon avalanche diode (SPAD) sensors. Optimised BSI SPADs with small pitch, high detection efficiency, low noise and broad spectral range have recently been developed. Digital processing placed under these SPADs has leaped to advanced digital 40/22nm nodes matching those adopted in state-of-the-art stacked-BSI CIS. Unlike CIS, SPAD pixels require no analogue processing and offer relatively large areas for embedded digital signal processing. This offers new potential for image sensor designers to implement direct Time of Flight (dToF) imaging and time-correlated single photon counting (TCSPC) on a massively parallel scale.  Power efficiency and timing uniformity represent a particular challenge of these devices given the high charge per pulse of detectors and large simultaneous power draw of time to digital converters operating at GHz frequencies. Huge data volumes generated by SPADs firing collectively at Giga-events/s in high ambient scenarios must be handled by novel sharing and time multiplexing of digital pixel processing resources. This talk will review some of these recent advances in stacked 3D SPAD pixel and sensor architectures including examples drawn from the author’s own work. Technology trends and future pixel scaling possibilities will be discussed.

Advanced manufacturing technologies originally developed for CMOS image sensors have catapulted single photon avalanche diode arrays into the mainstream of imaging leading to volume products in the 3D time of flight imaging and automotive LIDAR. Medical and scientific applications have been slower to emerge but are poised to leverage the wide spectral range, high detection efficiency, low dark noise, picosecond resolution and dense digital integration provided by these technology platforms. This talk will highlight CMOS SPAD solutions to a number of medical and scientific applications including Positron Emission Tomography (PET), fluorescence lifetime imaging for microscopy and cancer margin endoscopy, optical neural interfaces and Raman spectroscopy. The circuit architectures will be reviewed illustrating the symbiosis with 3D time of flight technology. The prospects for future advances exploiting recent 3D stacked process trends will be examined.

Single photon detectors such as single photon avalanche diodes (SPADs) have been traditionally deployed for low light sensing in scientific, radiation or microscopy applications. In the last few years, there has been a huge upsurge of interest in the use of SPAD detectors for low cost, mass market LIDAR for artificial reality (AR/VR) or automated driving assistance (ADAS). In these applications the detectors must tolerate high levels of solar background flux requiring a high dynamic range in the time domain rather than the charge or voltage domain. This requires the entire signal chain of the SPAD direct Time of Flight (dToF) sensors to be reconsidered from a legacy of scientific TCSPC electronics exploiting the sparsity of photon arrivals in low light conditions. A variety of solutions such as pixel combining techniques, partial histogramming and multi-event TDC architectures have been proposed. We will compare these approaches with respect to background conditions, laser power, angular and depth resolution and present the SPAD receiver challenges for both flash and scanning lidar systems.

This tutorial will highlight advanced modeling and simulation methods to estimate various performance metrics such as bit-error rate (BER), eye-opening, and jitter tolerance (JTOL) of state-of-the-art high-speed I/O interfaces. Specifically, the talk will address how to model interferences and noises present in I/O systems and estimate BERs using efficient statistical simulation techniques. Topics of interest include: modeling the nonlinear distortion, finite aperture, and noise in analog front-end circuits such as equalizers and clocked comparators; assessing the effects of power-supply noise and feedback latency in digitally-controlled timing circuits such as PLLs and CDRs; simulating the transient and steady-state behaviors of various calibration loops such as equalizer adaptation loops and offset calibration loops; and evaluating design trade-offs in ADC-based links.

Today’s SoC designs are neither purely digital nor purely analog; they are mixtures of both. As SPICE simulators face difficulty in handling such large circuits at the system level, modeling the analog circuits in SystemVerilog and verifying the whole system using digital verification flows such as UVM is becoming a common practice. This talk addresses ways to auto-extract models from analog circuits and run efficient simulations with them in an event-driven logic simulator like SystemVerilog.
It all starts with how we express analog waveforms. Using equations instead of points, the event-driven algorithm of SystemVerilog can be extended to analog simulations, even to transistor-level circuits exchanging voltages and currents. This also opens the door to automated ways of extracting models from circuits. Using a set of model templates both at the device level and at the circuit level, the models with SPICE-accurate characteristics can be auto-generated from the circuits. These analog models running in SystemVerilog can deliver up to ~100x speed-up’s compared to running SPICE.

The recent development in neural networks has required massive data transfer between memory and processing elements for data processing. This heavy data transfer leads to substantial energy overhead and limits the overall performance of the neural networks. Computing-in-memory (CIM) has attracted the research community’s attention because of the significant energy efficiency improvement by minimizing the energy-hungry data transfer. CIM designs can employ either analog computing or digital computing, while each has its pros and cons. In this talk, I will present the basics of CIM design and various challenges. After that, various state-of-the-art CIM macros will be introduced. I will also discuss analog and digital CIM macros and their applications. In the last part, I will present CIM designs based on emerging non-volatile memory devices and their applications.

Various battery-powered ultra-low power applications such as Internet-of-Things (IoT), wearable devices, biomedical devices, and tiny machine learning have opened up a new domain of integrated circuits design. In these applications, minimizing energy is the most critical research focus. Since embedded memories, dominated by SRAMs, occupy substantial power and energy in the IoT devices, designing energy-efficient embedded memories is a critical task for enhancing the lifetime of IoT devices. In this talk, I will present the basics in ultra-low power SRAMs followed by state-of-the-art ultra-low power SRAM design techniques. Several emerging applications of SRAM will also be introduced. Finally, I will discuss future directions in ultra-low power embedded memory for IoT applications.

Recent developments in artificial intelligence (AI) and machine learning (ML) have created a growing interest in neural networks for smart IoT devices. However, it is critical to design energy-constrained neural networks because of the limited energy supply. Many well-known neural network models are not suitable for IoT applications whose energy is from a battery or an energy harvesting device with a limited form factor. In this talk, I will present various design considerations for ultra-low power application-specific tiny ML accelerators for smart IoT devices, followed by introducing several energy-efficient tiny ML accelerators and computing-in-memory macros for smart IoT applications.

Histogram test and THD measurement of high-resolution(18 to 20 bits) ADCs require a sinusoidal source with THD ~ -140dBc. Bench-top generators can be used, but they are bulky. The alternatives are to use a band-pass filter to clean up a medium-accuracy(~ -80dBc) sinusoid from a DAC or to use a sinusoidal oscillator. In either case, a very low distortion filter core is essential. This work investigates techniques for realizing ultra-low-distortion band-pass filters and sinusoidal oscillators. 

Active-RC filters have a very low distortion because nonlinearities can be suppressed using a high loop gain. The main sources of distortion in an active-RC bandpass filter are (a) The nonlinearity of the output stage of the opamp used in the active filter coupled with the capacitance at the input of that stage; This is suppressed using a buffer between the first and the second stage of the opamp, (b) distortion contributed by passive components(integrating capacitors) in the feedback loop that is not suppressed by the loop gain; This is mitigated using distortion cancellation, and (c) output conductance nonlinearity of the opamp; This is suppressed using a gain-boosted cascode output stage. In oscillators, an additional distortion source is the modulation of the oscillator’s loss by the ripple in the output of the amplitude stabilization loop that is required for stable sinusoidal oscillations. A four-phase full-wave rectifier combined with second-order ripple filtering minimizes this effect.

Using the principles above, low-distortion band-pass filters and sinusoidal oscillators are demonstrated in a 0.6 μm process. With a 5.6V supply, the 1kHz/10kHz band-pass filter prototype has 60dB HD2 attenuation and -143dBc/-142dBc THD for a 10Vppd output. The 1kHz/10kHz oscillator has -133dBc/-111dBc THD for a 10Vppd output.

A technique is proposed for increasing the data rate transmitted through an inductively coupled chip-to-chip link by resetting the channel state variables. This allows the data rate to be increased well beyond what is implied by the channel bandwidth. In the proposed scheme, the two sides of the link are resonated at the highest possible quality factor, maximizing link gain, and minimizing interference. The transmit signal is a binary matched pulse which maximizes the received signal for a given transmitter voltage limit. High-efficiency switching transmitters can be used for this type of signal. The proposed technique can be applied to communication links in which channel state variables are accessible for reset. For increasing the data rate, it is shown that the proposed state-variable reset technique results in a higher signal-to-noise ratio of the received signal and a higher energy efficiency compared to reducing the quality factor to widen the bandwidth, using equalization, or using multi- level signaling. The technique is demonstrated on a chip-to-chip link with coupled 1.5 mm × 1.5 mm planar inductors separated by 0.5mm in a 0.18μm CMOS process. 500 Mb/s data rate is achieved over a link which has a band-pass bandwidth of 185 MHz.

LC VCOs are commonly used for RF carrier generation. A wide tuning range in a single VCO is desirable for covering multiple bands while occupying a small area. An octave tuning range enables continuous coverage of all lower frequencies by integer frequency division. LC VCOs are most often tuned using variable capacitor banks and varactors. Because of switch resistances in capacitor banks and poor quality factor of varactors, using only capacitors for tuning degrades the phase noise, especially at millimeter-wave frequencies. Variable inductors using series switches pose the same problem. Mutual coupling can be exploited to realize multiple resonant modes with different effective inductances without using switches. This allows a wider tuning range without substantial reduction in the tank quality factor. Topologies for multi-mode resonant structures and their performance will be described with examples from the literature.

Gate driver circuits to ensure proper turn-on and turn-off for power switches are essential parts of a power converter design. They become significantly challenging for multilevel converters where multiple switches are operated at active voltage domains. Recent favorable use of Gallium-Nitride (GaN) devices for power switches makes gate driving even more difficult as the switch performance and reliability are very sensitive to variations of the gate driving signals and power rails compared with traditional power MOSFETs. In this talk, the speaker will discuss different gate driving methods with a multi-level multi-inductor hybrid (MIH) converter as the demonstration prototype to address two key challenges in designing gate drivers: 1) providing level-shifted PWM signals to active voltage domains and 2) powering schemes for gate driver circuits. The design techniques of gate drivers in both discrete implementation and integrated circuits will be covered to provide the perspective and design guidelines in high-voltage integrated power converter design.

While integrated power converter is required in every modern electronic system, designing one that achieves both area- and power-efficient continues to be a big challenge in many engineering teams. In this talk, the speaker will discuss a good design flow and a number of useful techniques in designing integrated power converters that he has accumulated over the last ~20 years of his career. The flow includes a process of coming up with a converter concept; discussing topology trade-off; a general, fundamental, but intuitive loss analysis and optimization; and desgin verification. Design techniques include different circuit techniques and important layout considerations.

The need for an efficient power management solution has never been more critical across virtually all electronic devices and systems from low power to high power, smartphones to data centers, battery-powered components to renewable-energy-powered grids, and from stationary systems to aircraft. The key, common challenge for power management in these systems is to satisfy increasingly demanding requirements in terms of efficiency, size, reliability, and cost, simultaneously. This talk will present a unique flow of integrated power converter architectures, topologies, and circuit techniques to address this challenge. Particularly, the speaker will discuss his group research work on a family of hybrid converters that achieve high efficiency for high output power density and current density.

Due to the integration of everyday objects to the open network, securing private data and preventing its leakage has become one of the most important concerns in the Internet-of-Things era. Physically unclonable functions (PUFs) have drawn attention as one of the key security primitives for IoT devices since they can provide unique, random, stable, and unclonable hardware fingerprints for secure communications. In this talk, key design challenges and recent design trend of PUF are presented in two aspects: 1) random key generation with entropy sources and 2) stabilization of the generated keys. Then, recent examples of cost-effective PUF implementations enable by compact entropy source implementation and lossless stabilization schemes are introduced.

Near-threshold voltage (NTV) computing offers a promising approach to achieve high energy efficiency, but its voltage scaling is limited by its sensitivity to PVT variations. To achieve energy-efficient and robust operation at NTV, the following attributes are required for sequential circuits: 1) fully static operation, 2) contention-free transitions, 3) no redundant internal toggling to minimize power consumption and 4) minimum area overhead. To date, reported flip-flop designs with single phase clock experience residual internal clock toggling, and/or functional failure due to lack of attributes 1 or 2. In this talk, the key attributes for low power flip-flops are reviewed and recent flip-flop designs that satisfies all aforementioned attributes, which makes it capable of low power and low voltage operations at NTV, are introduced.

Bi-directional Device-to-device (D2D) wireless power transfer, a.k.a. reverse wireless charging or wireless PowerShare, has been a fancy selling point for the flagship smartphone models. Yet, the power level and efficiency of the current solutions are relative low, or the size and cost are constrained. The magnetic coupling coils, where are made by long wires, unavoidably have relatively large parasitic resistances. To increase the wireless charging power and efficiency, high AC voltages on the coupling coils are favorable for reducing their conduction losses. Prior arts design the DC-DC conversion and DC-AC inversion or AC-DC rectification separately. In this talk, we will present our hybrid power conversion topologies that combine and merge the DC-DC and DC-AC/AC-DC stages, for the next-generation D2D wireless fast charging. 

With the rapid growing demands on data transmission and processing in a world of big data and artificial intelligence, the power consumption of the information industry sees an exponential increase. Then, the energy efficiency of the microprocessors becomes more and more important, from both thermal and energy perspectives. Per-core dynamic voltage and frequency scaling (DVFS) technology is proven to be an effective way to improve the digital system energy efficiency. But, per-core DVFS requires high current density fast-transient integrated voltage regulators (IVRs) at the point-of-load (PoL) to enable and support it. Recently, the advanced 3D packaging technologies enable more design flexibility and topology innovations for the PoL IVRs. This talk will introduce our recent advances on PoL IVRs, including switching power converters as well as linear low-dropout regulators.

TIAs are employed in many different systems, from wireless transceivers to qubit manipulation and readout in quantum computing or as low-noise amplifiers in optical receivers front-ends.

In this talk a few TIA design examples will be presented, covering different type of applications.

Performance requirements change dramatically depending on the application, leading to a wide variety of implementation styles and circuit techniques.

TIAs can be broadly grouped into two categories, i.e. closed-loop and open-loop topologies. 

Closed loop TIAs generally have better frequency response precision and can achieve higher dynamic range, but typically have higher power dissipation and limited bandwidth.

Open loop topologies are preferred when very wide bandwidth or ultra-low power dissipations are required.

Nearly every wireless receiver includes a TIA after the down-conversion mixer.

In wireless sensor networks or Internet-of-Things (IoT), bandwidth is limited but power dissipation is reduced to a minimum, leading to ultra-low-power TIAs that consume only a few uW.

In 5G FR1 receivers, TIAs with tens of MHz bandwidth and very high dynamic range are required. Closed-loop architectures are dominant, often with complex op-amp architecture and with and power consumptions in the order of a few mW.

In 5G FR2 receivers, TIAs with hundreds of MHz to a few GHz bandwidth are used, mostly based on open-loop topologies with power dissipations of tens of mW.

To conclude the overview, TIAs for electro-optical interfaces will be presented. In optical receivers a low-noise TIA is required to amplify the current detected by the photodiode. These TIAs have tens of GHz of bandwidth and can consume up to hundreds of mW power.

Biological processes such as neuronal signaling and cell growth are among the most complex micro- and nano-scale processes in nature. Historically such processes have been studied at system level because there were no tools available to study individual components of the process. However, cellular-level interfacing is needed to provide better understanding of the brain and to develop more advanced prosthetic devices and brain-machine interfaces. With semiconductor technology innovations, much recent work has been focused on unraveling biological complexity, but also on driving new diagnoses, treatments and therapies that are tailored to the individual. One of the drivers behind those innovations is novel CMOS circuits enabling multi-modal, high-precision data collection and analysis at ultra-low power consumption. In this talk, I will present recent biomedical developments based on silicon technology, and I will discuss the requirements, materials, circuit techniques and design challenges of their ASIC and SoC platforms.

The ability to detect single photons with high sensitivity and precision is revolutionizing the image sensors field. Single-photon avalanche diodes (SPAD) not only are extremely sensitive, but they also retain with high accuracy the photon arrival time, which opens a whole new world of opportunities. Conventional image sensors circuitry is not anymore enough to manage this device, which requires a completely different readout chain.

In this lecture an overview of the SPAD potential, with pros and cons, will be addressed. Typical circuit topologies employed in SPAD-based image sensors will be described, along with some examples of applications and current trends.

3D imaging arrived to the mainstream products and gadgets very recently, but it is under development since more than 20 years. Now, it serves applications ranging from consumer to automotive, from industrial production to space exploration. There are several solid-state techniques enabling 3D sensing and imaging, among which time-of-flight (ToF) is one of the most prominent.

In this lecture, the different techniques, devices, and circuits needed to address the realization of a solid-state ToF sensor or imager will be discussed, highlighting the specific challenges, the different application requirements and existing architectures.

We are used to capture images with our eyes – and cameras – using only visible light: however, different wavelengths carry different kind of information. There’s an interesting part of the electromagnetic spectrum called the Terahertz region (approximately from 100GHz to 10THz) where, at the borders of photonics and electronics, it is possible to realize imaging with particular features. Indeed, the transparency of dielectrics, the presence of spectral fingerprints of materials, and the non-ionizing nature of the radiation gathered a lot of attention.

In this lecture the methods to perform sensing and imaging with THz radiation, in particular exploiting simple FETs in standard CMOS technology, will be analyzed. As the signal to be detected is very weak, it poses the challenge of ultralow noise readout: therefore, a number of circuit alternatives will be shown.

On-chip communication directly impacts the performance, energy efficiency, and area of systems-on-chip, multi-processors and highly-parallel accelerators, especially for emerging machine learning applications. In this talk, I will introduce a range of design options for on-chip interconnects, from point-to-point links to complex network topologies, starting from architecture to low-level circuit techniques. The presentation addresses base routing schemes and mapping of different protocol families, such as data-flow or address-map based communication, up to memory coherence traffic. Moving on to microarchitecture, it presents flow-control and arbitration requirements and options. I will then detail circuit-level considerations, with a focus on different synchronization strategies across multiple clock domains, including multi-synchronous, source-synchronous-clocking, and fully-asynchronous circuits, to finally introduce the potential of 3D-chip integration for on-chip communication.

Deep neural networks (DNNs) have emerged as a key approach to solving complex problems across many application spaces, including image recognition, natural language processing, robotics, health care, and autonomous driving. Designing custom hardware accelerators for deep neural networks is highly promising, as they offer significant performance and power advantages compared to general-purpose processors.  This talk presents a hardware-software co-design framework called MAGNet that takes an application specification as input and produces an ASIC accelerator along with valid mappings for running the target networks. It explores different data formats, quantization techniques, memory hierarchies, and dataflow. A new data format called VS-Quant, which employs a per-vector scaled quantization scheme that employs a two-level scaling scheme for achieving low-precision computation is discussed. It presents novel multi-level dataflows that achieve reuse across different operands to improve energy efficiency.

Deep Neural Network (DNN) use cases range have diverse performance and power targets. These are highly compute-intensive and have growing demands as DNN models get larger and more complex. Package-level integration using multi-chip-modules (MCMs) is a promising approach for building large-scale systems. While accelerators fabricated on a single monolithic chip are optimal for specific network sizes, MCM-based architecture enables flexible scaling for efficient inference on a wide range of DNNs, from mobile to data center domains. This talk explores the benefits of using MCMs with fine-grained chiplets for scaling DNN inference. It presents a 36-chiplet prototype MCM system for deep-learning. The MCM is configurable to support a flexible mapping of DNN layers to the distributed compute and storage units. Communication energy is minimized with large on-chip distributed weight storage and a hierarchical network-on-chip and network-on-package, and inference energy is minimized through extensive data reuse.

Cell-based, synthesizable mixed-signal circuits such as ADPLLs, ADCs, and LDO are gaining significant traction. This is fueled by the exponentially increasing number of DRC rules in advanced nodes, added restrictions on custom layout, and overall increase in design time for full-custom, analog designs. This talk focuses on different techniques for cell-based analog designs that are amenable to using existing automatic place and route tools to automate their physical design, thereby significantly reducing design time.

Efficient and robust wireless connectivity is a requirement for most IoT applications. The radios need to be low power while still providing sufficient range and co-existing with other radios that share the same frequency bands. Supporting wireless standards is key for adoption and ubiquitous integration with the existing wireless infrastructure, but is often at odds with ultra-low power radio design. This presentation will start with a review of ultra-low power receivers reported in literature, followed by an overview of recent design trends and a discussion of what the future holds for ultra-low power radios for IoT applications.

5G is the latest global wireless standard, which increases peak data rates and connection densities tenfold compared to 4G LTE. To achieve such a superior wireless link, 3GPP 5G standards utilize both sub-6-GHz and millimeter-wave (mm-wave) frequency bands with wider aggregated channel bandwidth; multiple-input, multiple-output (MIMO) techniques; and complex modulations. These approaches all demand stringent phase noise and spurious tone performance of the local oscillator (LO). This talk provides an overview of the major LO design considerations and low-jitter frequency synthesis techniques for 5G New Radio, focusing on millimeter wave frequency bands for handset applications. It starts with frequency generation requirements and LO topology comparison, and then focuses on phase-locked loop (PLL) architecture design. Finally, circuit design techniques for key building blocks will be elaborated, including phase detectors (PDs), oscillators, and frequency multipliers.

High performance fractional-N phase-locked loops (PLLs) are essential elements of any advanced electronic systems. In recent years, both analog and all-digital PLLs employing sampling or sub-sampling phase detector have gained popularity and demonstrated below 100-fs integrated jitter and superior figure-of-merit. This talk focuses on this PLL architecture and elaborates the advanced design techniques to achieve low jitter, low fractional spurs, fast locking, and low power operation. Both circuits design and digital calibration techniques will be presented in detail. In addition, recent advances in reference clock generation will also be discussed as it is crucial for high performance PLLs.

Besides the classic PC and Server applications, the ever growing new AI and HPC applications are driving even more data processing, hence leads memory growth. SRAM and DRAM has been and will continue to be the main supplier of data processing memory. But there’re opportunities to invent new memories to close the performance-density gap in the memory hierarchies. This talk will go through the memory hierarchy and touch upon different memory types and their applications. It’ll also analyze emerging memories such as MRAM, RRAM and FeRAM and how it’d replace eFlash for embedded non-volatile memories.

Integrated electronic-photonic co-design can profoundly impact both fields resulting in advances in several areas such as energy efficient communication, computation, signal processing, imaging, and sensing. Examples of integrated electronic-photonic co-design may be categorized into two groups: (a) electronic assisted photonics, where integrated analog, RF, mm-wave, and THz circuits are employed to improve the performance of photonic systems, and (b) photonic assisted electronics, where photonic systems and devices are used to improve the performance of integrated RF, mm-wave, and THz systems. In this talk, examples of electronic-photonic co-design such as photonic assisted near-field imaging, photonic-mmWave deep networks, and low power laser stabilization and linewidth reduction will be presented.

The typical hardware platform for neural networks operates based on clocked computation and consists of advanced parallel graphics processing units (GPU) and/or application specific integrated circuits (ASIC), which are reconfigurable, multi-purpose and robust. However, for such platforms the input data often needs to be converted to electrical domain, digitized, and stored. Furthermore, a clocked computation system typically has a high power consumption, suffers from a limited speed, and requires a large data storage device. To address the ever-increasing demand for more sophisticated and complex AI based systems, deeper neural networks with a large number of layers and neurons are required, which result in even higher power consumption and longer computation time. Photonic deep networks could address some of these challenges by utilizing the large bandwidth available around the optical carrier and low propagation loss of CMOS-compatible photonic devices and blocks. In this talk, a low-cost integrated highly-scalable photonic architecture for implementation of deep neural networks for image/video/signal classification is presented, where the input images are taken using an array of pixels and directly processed in the optical domain. The implemented system performs computation by propagation and, as such, is several orders-of-magnitude faster than state-of-the-art clocked based systems and operates at a significantly lower power consumption. This system, which is scalable to a network with a large number of layers, performs in-domain processing (i.e. processing in the optical domain) and as a result, opto-electronic conversion, analog-to-digital conversion, and requirement for a large memory module are eliminated.

This talk will cover principles and application of current mode design techniques for ultra low power transceivers/signal generators. Current mode design techniques are becoming popular in recent times due to emergence of beamforming and AI/ML applications. In this talk, a few novel constructs for current mode designs shall be presented that are implemented using 14nm CMOS FinFET technology for qubit state controller (QSC) used for next generation quantum computing applications. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power current-mode single sideband upconversion I/Q mixerbased RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.7μs and 73μs, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76x10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW.

This talk will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power currentmode single sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.7μs and 73μs, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76x10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW.

Multilevel signaling has extended the lifeline of wireline signaling beyond 100 Gb/s. But it’s SNR penalty has mandated much more sophisticated equalization that is more suitable for digital implementation. This presentation aims at bridging the gap between well-understood analog/mixed-signal solutions and today’s DSP-based solutions. Starting from traditional analog architectures, this talk will walk through the evolution toward today’s DSP-based equalization and provide the background for tomorrow’s sequence decoding.

Timing recovery techniques have evolved significantly over the last 25 years of high-speed link design. In the first decade, this evolution was motivated by technology scaling and scalability, where it gradually moved to a fully digital implementation from an analog PLL-based approach. However, the evolution in the last decade is motivated by the adoption of multilevel signaling. The emergence of MMSE as an alternative to 2X oversampled solutions is an example of such recent developments. This talk aims to bring designers up to speed on the state-of-the-art ADC-DSP solutions, explain their motivation, and finally conclude with silicon results to validate the performance improvement achievable in these architectures.  

The next-generation wireline and wireless systems promise wider bandwidth to enable a vast range of applications, including autonomous vehicles, virtual reality, and the internet of things. Such high data rates mandate precise clock generation to meet the timing budget. At the same time, flexibility to support multiple standards and scalability to meet higher integration density introduces additional dimensions to the clocking challenge. This talk will discuss recent circuit and architecture innovations to address these challenges. Starting from simple phase-locking concepts such as PLL, DLL and ILO, this talk will explain how the combination of these techniques is adopted in modern communication systems. It will also describe two example cases - i. A 28 GHz frequency synthesizer for 5G LO based beam forming, and ii. A flexible clocking solution for 10Gb/s to 112 Gb/s SerDes in 7 nm finFET technology.    

Piezoelectric vibration-to-electricity conversion provides a feasible solution to self-sustainability due to its relatively high power density, wider voltage range, and the compatibility with IC technology. In the past decade, we have seen a booming of various interface circuits developed for piezoelectric energy harvesting. The drastic difference between the operating speed of integrated circuits and mechanical vibrations provides a perfect venue for performing nonlinear switching and control in the interface operation with low power, allowing orders of magnitude of improvement in power extracting ability.

This tutorial will cover a wide range of state-of-the-art interface designs and MPPT methods for piezoelectric energy harvesting, while emphasizing the circuit implementation considerations. Specifically, after describing the basic full-bridge and half-bridge rectifiers, the Synchronized-Switch-Harvesting (SSH) technique that is the foundation of all modern nonlinear interface circuits will be introduced. Two major categories, namely, the open-circuit and the short-circuit structures, are then discussed in details. After that, the common MPPT algorithms and implementations will be reviewed. This talk will also cover topics such as non-resonant operations and multiple-input piezoelectric energy harvesting systems.

The size and complexity of recent deep learning models continue to increase exponentially, causing a serious amount of hardware overheads for training those models. Contrary to inference-only hardware, neural network training is very sensitive to computation errors; hence, training processors must support high-precision computation to avoid a large performance drop, severely limiting their processing efficiency. This talk will introduce a comprehensive design approach to arrive at an optimal training processor design. More specifically, the talk will discuss how we should make important design decisions for training processors in more depth, including i) hardware-friendly training algorithms, ii) optimal data formats, and iii) processor architecture for high precision and utilization.

Pretrained deep learning models are strong against computation errors up to some extent, and this has sparked numerous ways of deep learning acceleration through circuit design techniques. Examples include time-domain computing, charge-domain computing, and feature extraction using analog circuits. However, non-ideal characteristics of transistors unavoidably lower their accuracy compared to their digital counterparts. Even if small, this drop could limit their usage in real-world applications. This talk discusses how we can close this performance gap at each design hierarchy level.

On the other hand, deep learning is now actively employed for hardware design automation. Large-scale digital systems have greatly benefited from these efforts, but automating low-level circuit design might be just around the corner. This talk introduces recent advances in circuit design automation with machine learning, from topology generation to size optimization and layout generation.

Deep learning technology has made significant progress on various cognitive tasks, such as image classification, object detection, speech recognition, and natural language processing. However, the vast adaptation of deep learning also highlights its shortcomings, such as limited generalizability and lack of interpretability, also requiring manually-annotated training samples with sophisticated learning schemes. Witnessing the performance saturation of early models such as MLP, CNN, and RNN, one notable recent innovation in deep learning architecture is the transformer model introduced in 2017. It has two good properties towards artificial general intelligence over conventional models. First, the performance of transformer models continues to grow with their model sizes and training data. Second, transformers can be pre-trained with lots of unlabeled data through self-supervised learning and can be easily fine-tuned for each application.

Artificial intelligence (AI) and machine learning (ML) technology are revolutionizing many fields of study as well as a wide range of industry sectors such as information technology, mobile communication, automotive, and manufacturing. As more industries are adopting the technology, we are facing an ever-increasing demand for a new type of hardware that enables faster and more energy efficient processing for AI workloads.

Traditional compute-centric computers such as CPU and GPU, which fetch data from the memory devices to on-chip processing cores, have been improving their compute performances rapidly with the scaling of process technology. However, in the era of AI and ML, as most workloads involve simple but data-intensive processing between large-scale model parameters and activations, data transfer between the storage and compute device becomes the bottleneck of the system (i.e., von-Neumann bottleneck). Memory-centric computing takes an opposite approach to solve this data movement problem. Instead of fetching data from the storage to compute, data stays in the memory while the processing units are merged into it so that computations can be done in the same location without moving any data.

In this talk, I will briefly summarize the challenges of the latest AI accelerators focusing on the data movement issue mentioned above. Then, I will go through various processing-in-memory (PIM) architectures that can improve the performance and energy efficiency of the AI accelerators. I will also describe several notable circuit techniques on how we merge the logic into the memory and how we accelerate desired computations. Finally, I will propose a holistic approach to bridge the gap between the architectures and circuits and to make a practical and feasible PIM based solution for AI hardware.

The talk begins with a review of the fundamental and technological limiting factors to the spectral purity of integrated RF oscillators, and then proposes circuit solutions to break the phase noise barrier in silicon technology. Phase noise can be scaled by resorting to the multi-core approach, provided mismatches among multiple oscillators are carefully considered. As an example, a 16-core (voltage-controlled) oscillator demonstrates -130dBc/Hz at 1MHz offset from 20 GHz minimum phase. A more elegant and efficient approach is then introduced. Leveraging the series resonance of a tank, the remarkably lower resistance rises considerably the tank active power, thus enabling a remarkable improvement on the spectral purity. Two 10GHz BiCMOS VCOs exploiting the concept are proposed. The measured minimum phase noise is −138 dBc/Hz at 1-MHz offset with 600mW from 1.2-V supply. Experimental results demonstrate the lowest phase noise ever reported by fully integrated RF oscillators in a silicon technology.

The automotive industry is in the midst of a significant transformation. “CASE: Connected, Autonomous, Shared & Service, Electric” has been advocated as a trend. Along with this trend, automotive E/E (Electrical/Electronic) architecture will evolve from the current distributed architecture to a domain architecture and then to the future zone architecture in the autonomous driving era. The lecture introduces the requirement of automotive system design for in-vehicle devices and their key technologies, including processors for the infotainment system and advanced vehicle control. The lecture also covers automotive functional safety, security, and maintenance & upgrades with OTA(Over the air).

Electrical vehicles will become the standard in private transport the coming decade. Since the battery is still the main component that will determine cost and driving range, a good battery control is the main component in an eV system.

A battery management system consists of 2 components : a current measurement system and a voltage monitoring system. Both have their own specific problems.

We will first discuss the different techniques to measure current : using a shunt, a Rogowski coil or using a magnetic sensor.

Next the voltage measurement chain will be tackled including techniques for dealing with the high voltages of a battery pack.

In this lecture we will discuss the basics of charge pump design. Starting with the fundamental observation that half of the energy is lost when charging a capacitor, the principle of quasi-static charging is explained. From these charge balancing laws, the basic model of a charge pump can be derived together with the slow switching limit and fast switching limit. This on its turn leads to the PFM control loop to regulate the output power.

All this is illustrated with several examples like a Dickson Charge Pump, a series-parallel converter, the Fibonacci converter, … and more advanced techniques like multi-phase are touched.

In the second part, a real life design plan is shown where starting from the specifications a topology is developed and simulated.

Barometric pressure sensor are indispensable features in wearable consumer devices. Modern designs can sense absolute height difference of less than 8.5cm (1Pa), improving indoor navigation significantly and enabling new applications such as activity tracking and crash detection. In this talk, we will take a deep dive into the design challenges of readout chains for capacitive pressure sensors.

The main driving requirements are noise and power. To reach the demanding targets for wearable devices, heavy duty cycling and advanced analog front-end design is needed. But these are not the only challenges. Since they must be exposed to the atmosphere, pressure sensors in smartphones are often located in their outer cases, and have long connections to the main PCB. This leads to high demands on their PSRR and RF immunity. Both topics will be discussed, as well as several methods to improve the robustness of pressure sensor readout chains.

Magnetic sensors are everywhere, from the accurate current measurement applications over wheel speed sensors to magnetic switches that measure the angle of your laptop case. In the field of magnetic sensors, the Hall effect sensor plays an important role for its high linearity and since it is fully integrated in almost any semiconductor technology.

In this lecture we will cover the basics of a hall plate sensor, starting with the 1D hall plate and extending this to integrated 3D sensors. One of the drawbacks of a hall plate is its high offset. Techniques for reducing this non-ideality like quadrature layout and spinning will be elaborated.

A full analog readout chain will then be further discussed with an emphasis on the instrumentation amplifier including best design practices and simulation techniques. 

In this seminar, we will present a thorough review of the recent digital low-dropout voltage regulators (DLDOs). We have reviewed them in five aspects: control laws, triggering methods, power-FET circuit design, digital-analog hybridization, and single vs. distributed architectures. We then surveyed and benchmarked over 50 DLDOs published in the last decade. In addition, we have offered a new figure of merit (FoM) to address the shortcomings of the previously proposed FoMs. The benchmark provides insights into which techniques contribute to better dynamic load regulation performance. The survey and benchmark results are uploaded to a public repository. 

In the last decade, SRAM-based in-memory computing (IMC) hardware has received significant research attention for its massive energy efficiency and performance boost. In this seminar, first, we will introduce two very recent macro prototypes which achieve state-of-the-art performance and energy efficiency yet leverage very different computing mechanisms. Specifically, one adopted analog-mixed-signal (AMC) computing mechanisms (capacitive coupling and charge sharing), whereas the other adopted a fully digital approach. After this macro-level introduction, we will present recent microprocessor prototypes that employ IMC-based accelerators, which can perform on-chip inferences at very high energy efficiency and low latency. 

The number of connected devices is expected to reach 500 billion by 2030, which is 59-times larger than the expected world population. Objects will become the dominant users of next-generation communications and sensing at untethered, wireline-like broadband performance, bandwidths, and throughputs. This sub-terahertz 6G communication and sensing will integrate security and intelligence. It will enable a 10x to 100x increase in peak data rates. FPGAs are well positioned to enable intelligent radios for 6G when coupled with high-performance chiplets incorporating RF circuits, data converters, and digital baseband circuits incorporating machine learning and security.  This talk presents use of 2.5D and 3D heterogeneous integration of FPGAs with chiplets, leveraging Intel’s EMIB/Foveros technologies with focus on one emerging application driver: FPGA-based 6G sub-THz intelligent wireless systems.  Nano-, micro-, and macro-3D heterogeneous integration is summarized, and previous research in 2.5D chiplet integration with FPGAs is leveraged to forge a path towards new 3D-FPGA based 6G platforms.  Challenges in antenna, packaging, power delivery, system architecture design, thermals, and integrated design methodologies/tools are briefly outlined. Opportunities to standardize die-to-die interfaces for modular integration of internal and external circuit IPs are also discussed.   

System adaptivity has been studied since the mid-60s and recently there has been a surge in interest in self-adaptive systems, especially in the software engineering community,
with its main application is cybernetics. This talk introduces the concept of a self-adaptive system as it is extended to wireless communication, where channel characteristics are exploited to intelligently modify operation of the physical layer of the radio to optimize energy consumption and connectivity. The architectural and circuit foundations required to realize a wide-band “learning-based” transceiver architecture are detailed in the design and implementation of configurable PHY subsystems that can be dynamically programmed to realize intelligent radios. Current advancements in the application of AI/ML to wireless systems and how these may be leveraged at the PHY level are briefly discussed followed by an overview of future research required to build intelligently adaptive radio systems.

The use of millimeter-wave frequencies for 5G networks has been a primary contributor for transitioning Si-based phased array technology from R&D to real-world deployments. While the commercial use of millimeter-wave sensing so far has been dominated by low-cost, compact MIMO radars for automotive and industrial applications, the on-going wide deployment and advancement of Si-based phased arrays opens a new horizon of opportunities for sensing and event recognition. This talk will first cover the fundamentals and KPIs of 3D radar systems using phased arrays including associated key circuit design and packaging design techniques. Examples of such 3D radar systems at 28-GHz, 60-GHz and 94-GHz will be provided. Next, the presentation will describe how the full potential of such systems can be realized through synergistic co-design with algorithms and edge computing assets. Key examples of emerging applications based on these vertically integrated antennas-to-software/AI systems will be provided including multi-spectral imaging, 5G mmWave joint sensing and communications, and AI-based recognition of human gestures and concealed objects.

Over the last two decades, advancements on Si-based electronics enabled the development of wireless systems operating at millimeter-wave frequencies. Along the way, advanced package  designs and component integration technologies were crucial in enabling those systems to reach their full potential and, more importantly, achieve commercial impact. As we enter the maturing stage of 5G and start seeing the dawn of 6G on the horizon, mmWave systems are expected to play a growing role in high-throughput wireless communications and a large variety of sensing applications. This talk will first review key milestones in the history of mmWave module development with focus on phased arrays. The lessons learned from this journey will be described, with emphasis on antenna-in-package design and IC-package co-design. Then, emerging mmWave systems and applications will be described including the software-defined phased array, a multi-spectral imaging platform, and AI-based feature extraction from 3D radar. The presentation will conclude by outlining the next set of challenges that IC, package, and module integration technologies need to address to enable the realization of those system concepts and as compact “Antennas-to-AI” heterogeneous modules.

Machine learning (ML) is the driving application of the next-generation computational hardware. How to design ML hardware to achieve a high performance, efficiency, and flexibility to support fast growing ML workloads is a key challenge. Besides dataflow-optimized systolic arrays and single instruction, multiple data (SIMD) engines, efficient ML accelerators have been designed to take advantage of static and dynamic data sparsity. To accommodate the fast-evolving ML workloads, matrix engines can be integrated with an FPGA to provide the efficiency of kernel computation and the flexibility of control. To support the increasing ML model complexity, modular chiplets can be tiled on a 2.5D interposer and stacked in a 3D package. We envision that a combination of these techniques will be required to address the needs of future ML applications.

The modular partition into chiplets and the integration of chiplets in 2.5D or 3D forms offer a promising path towards constructing large-scale systems to deliver a performance comparable to single-chip integration, but without the high cost, risks and effort associated with monolithic integration. Industry has shown us what are possible with chipletization. However, for the technology to truly take off, we need three key elements to be in place: chiplets equipped with a standard interface, advanced bumping and packaging technology, and design automation. I will share our journey in conducting research on chipletization and the development of chiplets, all equipped with a standard-conforming, sub-pJ/b, synthesizable I/O interface. Through collaborations, we demonstrated multi-chip packages by tiling homogeneous chiplets and integrating heterogeneous multi-functional chiplets to efficiently scale up systems and improve their performance and versatility. Our lessons taught us that the success of chipletization must rely on an ecosystem that lowers the entry barriers, and the best practice in chipletization is to employ cross-domain endeavors that span system design, IC design, packaging, and assembly.