Distinguished Lecturer Roster

Dynamic device, circuit, and system parameter variations degrade processor performance, energy efficiency, and yield across all market segments, ranging from small embedded cores in an Internet of Things (IoT) device to large multicore servers.  This lecture introduces the primary variations during the processor operational lifetime, including supply voltage droops, temperature changes, transistor and interconnect aging, radiation-induced soft errors, and workload fluctuations.  This presentation then describes the negative impact of these variations on processor logic and memory across a wide range of voltage and clock frequency operating conditions.  To mitigate the adverse effects from dynamic variations, this lecture presents adaptive and resilient circuits while highlighting the key design trade-offs and testing implications for product deployment.

Deep neural networks (DNNs) are commonly used in artificial intelligence (AI) processors to achieve high-accuracy recognition and prediction functions for a variety of applications. However, DNN-based AI processors using a conventional (von Neumann) architecture face challenges in long latency and high energy consumption due to memory wall issue in data movement and large-volume computation. Computing-in-memory (CIM) or process-in-memory (PIM) methods have been proposed to improve computational efficiency by enabling parallel computing within the memory macro or array, thereby reducing the instances of memory access and suppressing the volume of intermediate data to be generated. In this talk, I will review recent progress and the challenges in circuit designs of SRAM and emerging memory (STT-MRAM, ReRAM and PCM) based CIMs for AI chips.

Memory has become one of the bottlenecks in the development of IoT and wearable devices with low energy consumption. This seminar addresses trends in the development of on-chip (embedded) nonvolatile memory (NVM) for energy-efficient IoT applications. The first part of this seminar will introduce a variety of nonvolatile memory (NVM) technologies, including eFlash, resistive RAM (ReRAM), phase-change memory (PCM), and STT-MRAM. This seminar will explore the challenges and silicon verified solutions in the design of low-power and high-speed circuits for on-chip NVM macros. The 2nd part of this seminar will explore the implementation of emerging memory beyond conventional memory applications, such as nonvolatile-logics (nvLogics) and nonvolatile processors for frequent-off intelligent IoT chips.

Internet of Things (IoT) devices are rapidly becoming common place in consumer, industrial, medical, automotive applications and elsewhere. In most cases, a network of multiple devices, called nodes, each one including sensors and actuators interfacing to the physical world, communicates wirelessly with a hub/base station, which, in turn, acts as a gateway to internet. This lecture introduces to the analog/mixed-signal hardware of the IoT devices and the hub. It discusses the most common sensors and actuators used in the network nodes, their signal conditioning electronics, the data acquisition/synthesis (ADCs/DACs), and briefly touches upon the embedded digital signal processing. A brief technical introduction makes the core topics accessible to the non-experts. Some case studies illustrating the practical implementations of IoT devices to a variety of applications and real products complement the technology coverage.

Demand for ultra-wideband data acquisition and real time processing systems handling analog signals in the GHz range comes from applications in high performance instrumentation, defense and infrastructure communication systems among others. In these cases, front-end circuitry and ADCs/DACs are rapidly getting integrated together with front-end digital processing, preferably in mixed-signal CMOS systems-on-a-chip. This lecture will briefly review some of the technical challenges faced by analog designers developing such systems along with some the technologies behind that. The performance demands, coupled together with limitations of the underlying technologies such as those of nanometer CMOS processes and die packaging, require a comprehensive design approach combining circuits and architectural innovation with algorithmic techniques. This lecture introduces some of the present engineering approaches being developed to tackle such challenges. 

Many emerging applications in wearable sensors, unattended ground sensor networks, and other Internet-of-Things (IoT) devices measure signals such as human physiochemistry, ambient temperature, or the presence of intruders - all of which are signals that do not tend to vary rapidly with time. In such systems, battery life is often dominated by radios - not because of large payloads, but rather due to the constant communication of small packets in order to maintain network synchronization. This presentation will discuss how wake-up receivers (WuRXs), if designed for bandwidths that support the average expected throughput needs of a given application, can be used to dramatically reduce average power consumption in such applications. Conventional wake-up radio architectures will be reviewed and analyzed for their strengths and weaknesses, followed by detailed discussions on state-of-the-art architecture and circuit techniques that can be used to improve sensitivity and/or reduce WuRX power consumption.

Wearable devices hold considerable promise to diagnose, monitor, and treat various medical conditions and/or track the real-time status of athletes. However, most current generation wearable devices only monitor a limited number of physical and electrophysiological parameters that are, in many cases, only peripherally related to many health conditions or fitness enterprises. Furthermore, many such wearable devices are large, bulky, and rigid, thereby precluding seamless integration into daily life.

Addressing these issues requires:  1) development of new sensor technologies that provide more actionable data in thin, flexible form factors; 2) engineering of supporting electronic infrastructure to condition, digitize, and wirelessly communicate data in an extremely energy efficient manner; and 3) new data analytics to process and understand newly generated data streams. This presentation will discuss emerging sensor technologies that can non-invasively monitor physiochemistry (e.g., glucose, blood alcohol concentration, and lactate) in thin, flexible, and energy-efficiency wearable devices, alongside a brief look at what kind of analytics are necessary to parse and understand this data. We will also cover integrated circuit building blocks and architectures that make acquisition and telemetry of sensed information so energy-efficient that that they can be easily powered from new local energy sources (e.g., wearable glucose biofuel cells). Such net-zero-power operation will ultimately enable devices that are completely autonomous and invisible to the user, to the point where users are virtually unaware of their wearable devices after placement – in other words, they are “unawearable” devices. 

Small, ultra-low-power integrated circuits afford new opportunities to sense and interact with the environment in new and exciting ways – for example by probing brain matter across arbitrary 3D geometries, to sensing temperature, humidity, or chemicals within or around the human body. Over the past several years, our group has demonstrated wireless ion sensing systems than consume less than 10nW of power, wireless glucose sensing systems powered directly by glucose biofuels, single-chip mm-sized neural implants with integrated electrodes, antennas, amplifiers, digitizers, stimulators, and power/telemetry units, and ultra-small and/or ultra-low-power building blocks including reference generators, DC-DC converters, and wake-up radios. This talk will review such contributions, and the challenges and opportunities moving towards self-powered mm-sized electronic systems.

Nowadays use of millimeter-wave spectrum for wireless communication is one of the most important technologies in next generation wireless such as 5G, IEEE802.11ad/ay, IEEE802.15.3d, etc. More than 10Gbps data rate is targeted for satisfying the social demand. This talk will explain basic system-level design of millimeter-wave transceiver as well as modeling and simulation for CMOS technology. Some design examples of millimeter-wave transceivers will be also introduced, which achieves 50Gbps and 120Gbps at 60GHz and 100GHz, respectively. The talk concludes with a discussion on future directions of millimeter-wave wireless communication, based on Shannon and Friis equations.

The wireless communication is one of the key technologies for realizing the future smart society. The conventional omni-directional wireless communication using microwave has been studied so far, and now the directional wireless communication using millimeter-wave (30-300GHz) is opening a new technology field of communication. The directional wireless communication using the millimeter-wave spectrum can accept spatial co-existence and multiplexing as well as use of wide frequency bandwidth. In this presentation, a millimeter-wave CMOS phased-array transceiver design is explained about phased-array architectures, phase shifters, power amplifiers, phase/gain calibration, measurement techniques, etc. The talk concludes with a discussion on future directions of millimeter-wave wireless communication, based on Shannon and Friis equations.

In this presentation, some design techniques for fractional-N digital PLL will be introduced to improve both jitter and power consumption for low-power wireless applications. A highly-linear and low-power DTC and TDC will be presented as well as system-level optimization. An isolated constant-slope DTC realizes 10bit 0.1mW operation with 26MHz reference clock, and sub-ps INL is achieved. The DTC-based AD-PLL achieves FoM of -246dB with 0.98mW power consumption and -56dBc worst-case fractional spur. For further power saving, duty-cycled FLL, sub-sampling/sampling switching, charge-recycling DTC, and transformer-based DCO for impedance peaking will be also explained, which achieves 0.265mw power consumption with FoM of -237dB at 2.4GHz. Finally, a DPLL-based ADC and a BLE transceiver using DPLL will be introduced.

Many IoT devices, especially those with very stringent energy constraints, operate in an intermittent manner. The device wakes up infrequently, performs a burst of activity, and goes back to a sleep/inactive mode. Clocking serves multiple functions in such devices. For example, during the burst of activity, a high frequency stable crystal oscillator may be required for the operation of a wireless transceiver. Alternatively, a low frequency real time clock (RTC) that is always ON may be needed to provide crucial sleep and wakeup timer functionality. As such, overall energy consumption in such IoT devices will remain high unless the clocks themselves consume very little energy. To address this challenge, my group has developed two complementary approaches. The first technique enables rapid startup of high-Q crystal oscillators whereas the second one develops a new low power oscillator sustaining circuit. While the latter reduces the power consumption of always ON oscillators, the former allows the clocks themselves to be aggressively duty cycled along with the other circuitry. This talk will describe both techniques and how they enable low power clocking.

Clever signal processing is capable of effectively resolving many of the challenges in analog, mixed-signal, and RF IC design posed by a variety of factors such as process variability, mismatches, device non-linearity. This approach takes different forms – post-processing of ADCs, pre-processing of DACs, digital pre-distortion of PAs, mismatch shaping, intentional random dithering, calibration etc.,  – invariably exploiting the abundant digital logic capabilities of modern CMOS processes to address the aforementioned errors. We have been developing several such techniques over the years. This talk will illustrate their application to open loop phase modulators which are widely used in wideband polar and IQ modulators, and in frequency synthesis, especially in very fine CMOS processes. Achieving low EVM and/or low spurious content is of great importance to these blocks, but they invariably suffer from device mismatches. The talk will describe an array of signal processing tecniques – dither based signal conditioning, least mean square (LMS) based spur cancellation etc. -  and how they were employed to achieve a sub-100fs fractional frequency synthesizer with spurious tones as low as –100 dBc on a 2.4GHz carrier.

Sharp, programmable, linear, integrated filters are enabling components for software defined and cognitive radio applications. However, they are difficult to realize: SAW and MEMS based filters are sharp and linear but not very programmable; active filters can be sharp and programmable but are not very linear; sampled charge domain filtering is sharp and programmable but the burden of the linearity is on the front end voltage-current converter. My group has developed a unique alternative that purposefully employs periodically time-varying circuit components to realize very sharp, linear, and programmable filters for use in RF front ends. This talk will describe how even simple 1st order RC filters can be converted into very sharp filters just by making one of the components, a resistor, vary periodically with time. The talk will show how our technique goes against conventional wisdom by exploiting sampling aliases rather than struggling to suppress them prior to sampling. It will describe how we applied the technique to realize RF front-ends and spectrum scanners with some of the best reported blocker suppression, linearity, and  power consumption. 

Power electronics can be found in everything from electric vehicles and industrial motors, to laptop power adaptors that hook up to wall outlets. While silicon still dominates the power semiconductor landscape, the recent onset of wide-bandgap semiconductor (WBG) devices promises low loss, higher frequency operation of converters leading to smaller, lighter power supplies. This talk will introduce the properties of high voltage (200-1200V) Si superjunction and WBG devices and discuss their relative merits. The common power converter topologies employed in power systems will be explored along with their associated gate-drive and protection circuits.

Power electronics can be found in everything from cellphones and laptops to gasoline/electric vehicles, industrial motors and inverters that connect solar panels to the electric grid. With close to 80% of electrical energy consumption in the US expected to flow through a power converter by 2030, innovative solutions are required to tackle key issues related to conversion efficiency, power density and cost. This talk will look at the trends in power electronics across different application spaces, describe the ongoing research efforts and highlight the challenges ahead.

With the advent of IoT technology, a wide variety of electronic devices are expected to be deployed in often inaccessible places. Keeping these space-constrained devices powered up for their intended lifetimes is one of the primary concerns in the widespread adoption of this technology. In this talk, I will look at the energy needs of IoT devices, discuss the power delivery architecture and examine the possibility of self-powered operation. The talk will delve into the basics of energy harvesting sources, storage mechanisms (batteries, supercapacitors) and the associated power management circuits needed (low-power DC/DC converters, chargers) to extend the operational lifetime of IoT devices. 

Power Amplifiers are a key component for any communication system. Combining energy efficiency, output power, gain, bandwidth and linearity in one single circuit requires a profound understanding of the different circuit trade-offs, the various system requirements and the technology limitations.

In this presentation, an overview of system requirements and PA architectures will be given, highlighting the strengths and weaknesses of each solution. Power combining and device stacking, being essential techniques to achieve high output power in low-voltage technologies, will be explained in more detail. Guidelines to design broadband and linear PAs will be discussed, complemented with many examples in nanometer CMOS (65nm-28nm) and FD-SOI (22nm). Finally, various circuit techniques to reduce AM/AM and AM/PM distortion in combination with high bandwidth will be discussed in more details and explained with several examples at 28GHz and 77GHz.

Using polymers or plastics as a flexible guided dielectric channel, together with mm-wave signals and Silicon chips, was recently proposed as a complementary alternative to optical and copper. Often referred to as Polymer Microwave Fibers (PMF), the mechanical robustness and EMI tolerance are key differentiators for this communication approach. Compared to optical communication, no EO/OE conversion is needed since the mm-wave signal is directly launched into the fiber with an antenna. Furthermore, the connectors have a much higher robustness compared to optical connectors. Compared to copper wireline, far less EMI issues arise since no metal is being used in the channel.

Several demonstrators have been developed both at Universities and companies, revealing the strengths and weaknesses of this approach. This presentation will give an in-depth discussion of the topic, discuss some of the implementation challenges and will give a good understanding of the benefits and drawback of PMF, and conclude with an outlook of the future of PMF. 

The maximum operating frequency of CMOS has steadily increased over the past thirty years and extrapolations would predict THz circuits in CMOS soon. Compared to other technologies, CMOS does offer integration complexity paving the road for entire THz systems. As such, potential applications such as near-field scanning, quality control, spectroscopy and imaging could be pushed to the consumer market.

However, CMOS scaling also resulted into thinner interconnects with higher intrinsic resistance which in turn limits the maximum operating frequency. On the other hand, one could go beyond the fmax-limit by exploiting the non-linear behavior of a transistor. This concept is used already in frequency-doubler and -triplers and can be extended to entire transmitters and receivers. This talk will highlight some of these challenges when designing circuits in CMOS in the THz (300GHz-3THz) frequency band. Several examples in 40nm and 28nm CMOS at a frequency range from 200 to 620GHz will be discussed.

The ability to allow predictive, proactive, personalized and preventive and participatory healthcare analytics through complex information extraction from bio-molecular level to physiological signal monitoring can have transformative impact in healthcare in future. However, while wearable technologies are maturing with time, extracting bio-molecular information that relies on protein or genetic material is still largely centralized laboratory based. Dominated by optical-based detection technologies, these end-to-end systems are large, bulky and expensive with a complex arrangement of various optical components such as lenses, filters, collimators whose functionalities haven’t changed fundamentally in the last 50 years.

In this talk, I will present approaches that allow elimination of all external optical elements for mm-scale, fully ‘optics-free’ single chip complex optical systems. In an absolutely no-change in CMOS fabrication we will show how integrated metal interconnects in the deep sub-wavelength regime can allow highly scalable and complex nanoplasmonic elements operating in the visible range and integrated in the same substrate as the integrated electronics.  In a series of demonstrative examples ranging from mm-scale, highly multiplexed, pill-sized bio-versatile molecular sensors 100-fM levels of DNA and protein sensitivity to optical spectrometers, I will try to show how this nano-optics/electronics co-design approach opens up a new co-design space across the optical, electronic and signal processing layers. By allowing new system properties that is greater than sum of its parts, this can eventually lead to a new class of intelligent, distributed, low-power sensors for future diagnostics, health monitoring, environmental safety, food and water quality monitoring. 

Future mm-Wave systems are expected to operate in a complex and heterogeneous environment extending from the electromagnetic propagation channels right up to the network layers. As disjointed spectral bands open up across 28-100 GHz for 5G applications and beyond, spectrally agile, robust mmWave front-ends that can allow dynamic reconfiguration in large scale mmWave MIMO arrays can have a transformative impact in spectrum efficiency and deployment of such 5G systems.

While this involves a series of challenges from the antenna to the transceivers I will highlight two specific directions in this talk. These emerge through a multi-port transceiver and multi-port antenna framework that allow each element to assume properties distinct from classical array architectures. Firstly, I will discuss the challenges of enabling a transmitter front-end particularly the power amplifier for such a spectrally-agile mmWave system. I will discuss multiport architectures that can allow simultaneously broadband, high power and high back-off efficient transmitter front-end, properties that typically strongly trade-off with each other. In the next part of the talk, we will discuss how such multi-port transceivers can be co-design and co-integrated with multi-port antennas to allow such spectrally-agile architectures, In addition to extremely high bandwidths, these architectures allow element level programmability needed for multi-band periodic arrays. These include the ability to reject interferers passively directly at the element antenna surface, reconfigure individual antenna patterns, and allow frequency, spatial, pattern and polarization diversity in scalable arrays.

Silicon-based Terahertz systems is a field that is only about a decade old. In this time, we have seen a phenomenal growth of silicon systems operating at THz frequencies for a wide range of applications in sensing, imaging and communication. It can be argued that both the ‘THz gap’ and the ‘technology and applications gap’ is closing in meaningful ways in the THz range. Technologies beyond 100 GHz focusing on sensing, imaging and wireless back-haul links are getting attractive as we enter into a new area of highly dense network of autonomous systems requiring ultra-high speed and reliable links.

In order to move beyond this inflection point as Moore’s law continue to slow, I will discuss why we need to look beyond the classical ‘device’-level metrics of efficiency and sensitivity of THz sources and detectors towards holistic ‘system’ level properties such as scalability and programmability. Such properties are critically important for applications in sensing and imaging, as evidenced across sensor fusion technologies across mmWave, IR and optical frequencies. The ultimate programmability in THz sources and sensors is one that can synthesize or receive THz fields with arbitrary configuration and spectrum. In this talk, I will highlight approaches that cut across electromagnetics, circuits, systems and signal processing, to allow for such reconfigurability in THz signal synthesis and sensing, yet realized with devices that are themselves not very efficient. Incorporating, such programmability across the three field properties of spectrum, beam pattern and polarization, I will comment on what could be the major directions for the field in the coming decade.

A gate driver IC is an important circuit bridging the voltage gap between control ICs operating at less than 5V and the power electronics operating above 100V. The conventional gate driver IC, however, just turns on/off the power transistors and shows the trade-off between the switching loss and the switching noise of the power transistors. In addition, the conventional gate driver IC need to be customized for a large variety of power transistors. To solve the problems, we proposed a programmable general-purpose digital gate driver IC, which dynamically changes the gate drive current during the turn-on/off transient with digital control bits. In the developed gate driver IC fabricated with 40V, 0.18um BCD process, the 6-bit gate control signals with four 160-ns time steps are globally optimized using a simulated annealing algorithm, reducing the switching noise by 37% and the switching loss by 47% at the double pulse test of 300V, 50A insulated gate bipolar transistor (IGBT). The gate driver is also applied to a half-bridge inverter, where the gate driving waveform is changed depending on the load current.

Integrated voltage regulation is critical to the energy efficiency in every systems ranging from high-end processors to ultra-low power IoT devices. Challenges of the integrated power management circuits include the large number of voltage domains, DVFS per domain, large current transients, and wide dynamic range of current loads. In addition, IoT systems present new challenges to the voltage regulators, keeping the high power conversion efficiency at the ultra-low input voltage ( < 0.1V) and/or the ultra-small output current ( < 1uA). In this talk, I will present several circuit designs of voltage regulators for IoT systems, including a sub-0.5V digital LDO / digital-analog hybrid LDO, a sub-0.5V-input buck converter, and a sub-0.1V-input boost converter for the thermoelectric energy harvesting.

The organic electronics enables flexible, large-area, and distributed sensor and/or actuator array and is suitable for the wearing-unconscious devices used in biomedical and healthcare applications.

Power delivery to ultra-thin flexible devices with the thickness of 1um to 10um, however, is a challenge, because wired connections and rigid battery are not allowed. To solve the problem, novel flexible devices for wearable healthcare applications with the energy harvesting or the wireless powering using organic circuits are proposed and demonstrated. In this talk, I will show an insole pedometer with piezoelectric energy harvesters, a fever alarm armband with solar cells, and a wet sensor sheet in a diaper with wireless powering.

Wide power-performance adaptation is becoming crucial in always-on nearly real-time and energy-autonomous integrated systems that are subject to wide variability in the power availability and the performance target. Adaptation is indeed a prerequisite to assure continuous operation in spite of the widely fluctuating energy/power source (e.g., energy harvester), and to grant swift response upon the occurrence of events of interest (e.g., on-chip data analytics), while maintaining extremely low consumption in the common case. These requirements have led to the strong demand of a new breed of integrated systems having an extremely wide performance-power scalability and adaptation, beyond conventional voltage scaling or adaptive parallelism. In this talk, new techniques that drastically extend the performance-power scalability of digital circuits and architectures are presented. Silicon demonstrations of better-than-voltage-scaling adaptation to the workload are illustrated for both the data path (i.e., microarchitecture) and the clock path. Adaptation to a very wide range of energy/power availability is also discussed, presenting demonstrations of always-on systems (e.g., microcontrollers, power management units) with power down to sub-nW, and duty-cycled operation down to pW range. Several silicon demonstrations are illustrated to quantify the benefits offered by wide power-performance adaptation, and identify opportunities and challenges for the decade ahead.

The historical 100X/decade energy down-scaling is currently being threatened by the end of Moore’s law, and the limited prospective energy gains from approaches that have been already exploited extensively (e.g., heterogeneous systems, ultra-low voltage, parallelism). Major shifts from traditional sensing/processing paradigms are now mandatory, and new design dimensions that enable further energy reductions need to be explored, to sustain continuous miniaturization, lifetime and cost improvements.
In this talk, energy-quality (EQ) scalable circuits and systems are introduced as a fundamental direction to continue the historical exponential energy down-scaling. The CAS community is currently focusing on this new field, which is also the theme of major journal special issues. EQ-scalable systems dynamically and explicitly trade off energy and quality from sensor to circuit, architecture, algorithm, and up to system level. Recent and novel approaches are discussed to minimize the energy at run time, based on the actual quality target that is set by the specific task, the context, and the specific dataset at hand. Quality is treated as an explicit knob, eliminating the quality slack that is traditionally imposed by worst-case design across different applications, contexts, datasets, and the pessimistic design margin to counteract process/voltage/temperature variations. Interesting convergence with machine learning and other important applications is discussed to provide an insight into the inter-dependence of algorithms, architectures and circuits. Several silicon demonstrations are illustrated to quantify the benefits offered by energy-quality scaling, and to describe the challenges that need to be solved to fulfill its potential.

Batteries pose fundamental threats to the further advancement of systems for ubiquitous sensing and intelligence (e.g., Internet of Things, devices for healthcare, smart objects/systems). Batteries are indeed a major cost and form factor bottleneck in single-chip integrated systems, and will also have a very heavy environmental impact when deployed (and disposed) at the expected scale of one trillion connected devices.
In this talk, state-of-the-art techniques for battery-lightweight and battery-less integrated systems with always-on operation are introduced. From a top-down viewpoint, system architectures are introduced to enable continuous adaptation to workload and harvested power/battery energy availability. Time- and event-driven frameworks are introduced and exemplified with several silicon demonstrations, along with duty-cycled and always-on schemes. From a bottom-up perspective, advanced circuit techniques are introduced to enable uninterrupted operation under uncommonly wide range of available harvested power, and/or very limited battery energy. The talk covers all major sub-systems along the on-chip signal chain, from energy harvesting to power delivery, analog interfaces, digital processing, and higher-level signal sensemaking. Edge computing, machine intelligence and in-memory computing are discussed as crucial enablers of continuous event monitoring and efficient energy usage at the system level. The related concepts are exemplified by integrated prototypes from industry and academia.

Security is finally being generally perceived (and often required) as an important attribute of hardware systems, as a result of several breaches and vulnerabilities that have been brought to the attention of the general public. Hardware security is now progressively becoming closer to ubiquitous in space and always-on in time, as the related building blocks and sub-systems need to be an essential part of any integrated system down to tightly power-constrained systems (e.g., nodes for the Internet of Things).
In this talk, pervasive hardware security is discussed in a broad sense, encompassing methods that assure security in every System on Chip (SoC), as well as in critical SoC components. From an SoC viewpoint, recent trends in energy efficiency are analyzed and put in perspective to identify the opportunities to embed security solutions down to low-end SoCs and in an always-on fashion. From an SoC component viewpoint, immersed-in-logic security primitives are discussed to highlight how security can be pervasive within each component, while keeping the system integration effort to a minimum. Cost-aware design methods are also discussed, being cost a major factor that decides whether a security feature is incorporated in real-world systems or not. Several silicon demonstrations are illustrated to quantify the benefits and the limits of existing techniques, and identify opportunities and challenges for the decade ahead. At the end of the talk, fundamental directions on how to make hardware security more pervasive and unceasing are discussed.

Over the last few years, a significant growth of the research involving the use of microwaves to image the human body has been taking place. Among the many examples of ongoing research, the use of microwaves for breast cancer diagnostic imaging has seen an increasing interest. Ultra wideband microwave radar imaging can effectively complement conventional diagnostic techniques, e.g. X‐ray, MRI, ultrasound, yielding higher sensibility and specificity, lower cost, and smaller size, hence emerging as an enabling technology for mass screening programs. Ultra wideband radars can be realized in different technologies, discrete or fully integrated. This talk investigates the typical system and circuit-level challenges of such radars, and discusses some implementation examples. The talk presents innovative circuit solutions addressing the challenges set by the ultra wideband frequency range of operation of the radar transceiver. Due to their broadband operation, such design techniques may find application in other wideband systems.

Integrated magnetic transformers are becoming ubiquitous in mm-wave and RF systems, while also finding application in fully-integrated dcdc converters. This talk will cover the fundamentals of the transformer operation spanning from the underlying physical principles, to the link between the magnetic parameters (inductances and magnetic coupling) and the geometry of the device, to its use in the design of building blocks like LNA’s, PA’s, VCO’s, etc. The advantages and possibilities of using a transformer for the implementation of baluns, impedance transformation networks, higher-order resonant networks, feedback circuits, etc., will be highlighted.

The talk will deal with the design of low-phase noise voltage-controlled harmonic oscillators (VCOs) implemented in bipolar technologies. The design challenges related to achieving minimum phase noise for a given set of technology parameters (supply voltage, metal stack, varactor devices, etc.) will be discussed with particular emphasis to attaining low phase noise while using varactor diodes, to the use of magnetic transformers in the resonator, and to the selection of the most appropriate oscillator topology. Effective techniques to tackle such issues will be illustrated. Design examples of VCOs operating in the K-band and suitable for 5G applications will be presented.

Cellular technology has witnessed five generations of evolution - the mobile UE-era ushered in by 2G (GSM/EDGE), to the future smart-phones that will powered by the enhanced spectral efficiency of 5G. Each 'G' improved the user experience while introducing new hardware design challenges. I compare 2/3/4/5G system requirements, derive key TX/RX/LO circuit specifications, and highlight the differences in circuit topologies suited for these contrasting specifications. Using this framework, circuit techniques to handle a diverse range of problems such as low phase-noise oscillators, improved blocker tolerance, single-RB linearity will be introduced.

The explosive growth services delivered via the internet onto the mobile handset has result in an insatiable demand for higher data-rates. Millimeter-wave CMOS radios – a research topic for over a decade – is now finally on the cusp of large-scale deployment. In this talk I will describe the challenges and state-of-the-art in circuits and architectures for 28GHz/38GHz 5G NR transceivers targeting user-equipment or UE applications.

Modern SoCs for advanced applications are integrating an increasing number of phase-locked loops (PLLs) into a single silicon die. 5G transceivers require multiple PLLs to implement complex schemes of carrier aggregation and MIMO. Multi-core processors also have to use many PLLs to generate independent clock frequencies for each core to operate at the optimum performance. With this trend, an area-efficient design of PLLs becomes more important. In this point of view, i.e., the efficiency in the use of silicon, ring-oscillator-based digital PLLs (DPLLs) have obvious merits over conventional LC VCO-based charge-pump PLLs. Ring-oscillator-based DPLLs also have an advantage in terms of the scalability with new CMOS technologies. They also can be implemented in some CMOS technologies where high-quality metal layers for inductors are not available. Despite foregoing merits, their poor jitter performance has limited their popularity in high-performance applications that generally require a clock signal having an ultra-low jitter. This lecture introduces recent architectures of low-jitter ring-oscillator-based DPLLs and presents key enabling circuit techniques to resolve their problems, such as thermal and flicker noises of ring oscillators, reference spurs, and fractional spurs. Finally, we discuss the limit of ring-oscillator-based DPLLs and the possibility of their adaptation to high-performance applications.

As the data rates of both wireless and wireline communication systems increase, the generation of millimeter-wave-band (mmW-band) signals that have ultra-low phase noise becomes more important for the design of the transceivers. The standard of the fifth-generation (5G) mobile system defines new radio frequencies in mmW bands from 24 to 40 GHz. To support high-order modulations, such as 256 QAM, the value of the EVM must be reduced to less than –30 dB, implying that mmW-band local-oscillating signals must have an extremely low IPN, e.g., less than −36 dBc. Similarly, to satisfy the Nyquist criterion and minimize the effect of channel mixing, direct RF-data converters using high-speed analog-to-digital converters (ADCs) also require mmW-band clock signals that have very low RMS jitter. The demands on the performance of the ultra-low jitter for mmW-band signals also have increased recently in advanced, high-speed serial links, in which the target data rates have increased to more than 100 Gb/s. As shown above, mmW-band signals are used in many different advanced applications, but they commonly are expected to have sub-100 fs RMS jitter values. This lecture introduces recent architectures of frequency synthesizers that can generate ultra-low-jitter mmW-band signals, based on a cascaded architecture consisting of a ultra-low-jitter GHz-range PLL and a wideband mmW-band injection-locked frequency multiplier.

Continuous increases in the data rates of communication systems demand further improvement in the jitter performance of clock signals. To date, conventional phase-locked loops (PLLs) using an LC-type voltage-controlled oscillator (LC-VCO) have been used the most widely in practical applications. However, the critical problem of LC-VCO-based PLLs is a large silicon area. Ring VCO-based injection-locked clock multipliers (ILCMs) are considered as an alternative solution. In ILCMs, the phase of the output edges of a free-running VCO is corrected naturally by periodically injected reference signals. This phase-realignment mechanism of an ILCM is capable of creating a much higher cutoff frequency of the noise transfer function (NTF) of the VCO compared to conventional PLLs, thereby resulting in the much greater suppression of the jitter of ring VCOs. Despite the superiority of ILCMs in the reduction of the jitter of ring VCOs, ILCMs have a critical problem in that the performances of RMS jitter and reference spur are degraded significantly due to PVT variations. This problem asks for intensive background calibration techniques that can remove any phase errors of ILCMs in a real-time fashion. This lecture presents ring-VCO-based ILCMs that can achieve a low reference spur as well as a low RMS jitter and the design of versatile background calibration techniques that can help ILCMs maintain good jitter performance.

Piezoelectric energy harvester (PEH) is one of the most promising candidate for ambient vibration energy scavenging for ubiquitous miniaturized Internet of Things (IoT) devices. Due to the PEH inherent capacitance, the extractable AC-DC electrical power in traditional PEH interface using full-bridge rectifier (FBR) is limited. Existing PEH interfaces generally employ non-linear techniques such as the parallel-synchronized-switch harvesting-on-inductor (P-SSHI) and fractional open circuit technique to enhance the extracted power and achieve efficient maximum power point tracking (MPPT). However, they typically require bulky external high-Q inductors to extend the damping duration while inducing excessive device voltage stress during MPPT. This talk will focus on the discussion of capacitive PEH interfaces for flipping the PEH voltage for energy extraction improvement. It will first cover the basic operations of capacitive PEH interfaces and provide the fundamental analysis on its performance limits. The design tradeoffs between the achievable extracted energy and the different loss mechanisms will be outlined. System level implementation of maximum power point tracking (MPPT) will also be discussed.

The recent wireless sensing and emerging Internet-of-Thing (IoT) market have enabled the development of miniaturized systems with different application requirements. While highly efficient power management is mandatory to ensure the system performance and operation lifetime, on-chip inductive power converters generally exhibits increased manufacturing cost despite of their higher achievable power densities. Due to the full integration together with high energy efficiency and adaptability, reconfigurable switched-capacitor (SC) DC-DC converters are promising for ultra-compact on-chip power solutions. This talk will first cover the basic operations and control methodologies of SC DC-DC converters. It will then introduce the conventional SC DC-DC topologies, followed by the fundamental analyses and different loss mechanisms. Advanced reconfigurable SC DC-DC converters capable of systematic multiple rational voltage conversion ratio (VCR) generation and their fundamental limits will also be proposed, and further compared with the state-of-the-art. Adaptive gate driving techniques with consistent switch driving voltage while preventing reversion loss under wide voltage dynamics will also be introduced. These techniques enable highly efficient SC power converters with better SoC integration for next generation ultra-compact low-cost IoT devices.

Common-mode rejection ratio (CMRR) is a fundamental consideration in the design of instrumentation amplifiers (IA). This talk studies the CMRR consideration with focus on the enhancement techniques. For AC-coupled IAs, the CMRR is often dominated by the mismatch of passive components, which can be improved by a modified chopping structure and impedance trimming. Theoretically, by cancelling the CM current, the CMRR can be improved structurally. The idea can be realized with a dedicated CM loop which replicates the input CM voltage along with the DM path, eliminating the generation of CM current. Moreover, the input CM impedance is improved simultaneously due to the elimination of CM current, which is typically required by IAs interfacing with high-impedance sensors, e.g., dry-contacted electrodes, accelerometers, etc. Demonstrated IA design examples are discussed.

Power-supply noise (PSN) is a key consideration that determines the performance as well as functionality of ICs, especially for modern SoCs with significantly increased scale, level of integration and driving complexity with sophisticated voltage and power controls. Externally measured PSN is inevitably distorted by packaging, PCB, etc., therefore, on-chip or on-die measurement of PSN is highly demanded with large bandwidth, high accuracy and high frequency resolution, which is extremely challenging. Moreover, clean supply is not available in this scenario. This talk overviews the on-chip PSN analyzer techniques, where the subsampling-based approach is promising due to the relaxed bandwidth constraints. However, the accuracy and frequency resolution are fundamentally determined by the number of averaging points, resulting in long measurement time. Multi-slice architecture, time-based quantizer and compressed sensing techniques are discussed with a 20GHz PSN analyzer design example, where significantly improved measurement accuracy and speed are demonstrated in addition to the system scalability.

Design of integrated circuits under near-/sub-threshold supply voltages is driven by the continued technology scaling as well as the increased demand on energy efficiency. Comparing with digital design that can often be compensated from system level, subthreshold analog design relies more on circuit-level techniques. This talk overviews the state-of-the-art subthreshold analog design techniques. Low-voltage design considerations are discussed along with several 0.1V-0.3V OTA and ADC examples. An evolutionary approach from matured amplifier topologies to inverter-based implementation is presented, which has been exploited and demonstrated in the design of near- and/or sub-threshold amplifiers, regulators, integrators and ΔΣ modulators. The potential of time-domain signaling in low-voltage design is also discussed.

SAR ADCs are coming of age due to the mostly digital implementations where the benefit of advanced CMOS technologies can be generally brought into ADC designs. Time-domain signaling is also promising since the speed and time resolution are both scaling favorable. Therefore, the SAR ADCs with time-based comparator have attracted significant interest in recent years. Nevertheless, comparing with oversampled converters where the unique property of VCO, the first-order noise shaping, has been used to enhance the system, Nyquist converters uses only the bit decision of time-base comparison. This talk introduces the concept of oscillation-cycle information in VCO-based comparators. With rigorous analysis, the number of oscillation cycles (NOC) can be generally exploited as a parallel coarse quantization with a large signal, and/or as a quantitative indication of metastability with a small signal. Moreover, the NOC is inherent and of little cost in hardware, power and area. The demonstrated VCO ADCs exhibit significantly enhanced linearity and robustness, comparing with their voltage-domain counterparts. This talk discusses also a closed-form metastability analysis of VCO-based comparator, introducing the metastability depth as a quantitative measure of metastability.

Facing a growing number of patients with neurological disorders, there are only limited therapeutic pharmacological measures which provide only temporary and mild amelioration of the devastating symptoms of these disorders. The use of electrical stimulation of the brain is a treatment option for patients with severe treatment-resistant disorders. Current deep-brain stimulation (DBS) approaches are hindered by inadequate technology that is low-precision and bulky, power-inefficient, and of limited diagnostic utility. The seminar will discuss a high-precision implantable neurotechnology for closed-loop neuromodulation of functional networks of the human brain. Key features of the technology are: 1) sensing from a high number of channels, 2) sensing concurrent with stimulation for true closed-loop operation, and 3) real-time secure wireless data telemetry. The proposed neurotechnology could revolutionize brain therapies in efficacy, size and cost of medical implants.

Technology scaling is power-limited, so compute energy efficiency improvements have to come from chip and system architectures. Increasing application diversity also argues for a more flexible compute architectures, further emphasizing the need for energy efficient design methods. This includes not just chips, but system solutions and dealing with miniaturization and complexity considerations. This talk will therefore discuss design methods for digital chip and system design, provide a detailed example of fixed-function accelerator architecture study, discuss several chip examples for baseband communications processing, and discuss system integration techniques ranging from next-generation medical implants to next-generation wafer-scale chip packaging. These applications further reveal opportunities in system-level design automation that would help address design productivity and system assembly challenges.

The power generation of transistors drops as we move to higher frequencies. At the same time, the free space propagation loss increases, demanding more radiated power from the system. The loss of passive elements in the circuit increases as well, making functions such as oscillation or radiation even more challenging. In order to boost the limited power, multiple sources need to be coupled together in an array structure. However, the significant loss of the coupling circuitry and phase shifters at mm-wave and terahertz frequencies hinders the implementation of large and efficient radiator and phased arrays. Scalable standing wave array structures are proposed based on efficient low-loss coupling schemes in order to boost the power and operation bandwidth. Furthermore, we present a practical approach to maximize Equivalent Isotropic Radiated Power (EIRP) of the source by optimizing influential parameters of the radiation apparatus. Finally, we demonstrate a new phase shifting method based on combining standing and traveling waves and show how it can achieve significantly higher phase shifting range and bandwidth.  Using all these methods we present coupled-oscillators, scalable radiator arrays, and phased arrays with record beam steering range, tuning range, and output power among relevant published works at mm-wave and terahertz frequencies.

In recent years many new mm-wave applications and standards have been emerging. These systems are mostly a response to the ever-growing demand for higher data speed, higher image resolution, and better sensing systems. The same trajectory to THz and higher frequencies will likely to continue in future for higher performance systems. Therefore, it is vital to understand the limit and capabilities of the fabrication platforms specially when the operating frequencies are getting close to or even surpassing the maximum oscillation frequency (fmax) of the transistors. In this talk we will discuss and present three transistor limits for oscillation frequency, harmonic generation, and power amplification. Using these analyses, we have implemented oscillators and amplifiers with record breaking DC-to-RF efficiency and output power at mm-wave and THz frequencies.

Accurate, stable and wideband mm-wave and terahertz sources prove to be essential for coherent data link, active sensing, and radar. The high frequency of operation creates major challenges for implementing such sources such as low tuning range and output power of voltage controlled oscillators (VCO), small locking range for injection locked frequency dividers, and in general high noise level and power consumption of frequency synthesizers. We present a mode switching technique to significantly increase the tuning range of the VCO’s at 200GHz and above. Moreover, a Colpitts-based active varactor (CAV) and a frequency divider with three-phase injection are proposed to reduce the effective loss of the varactors and increase the tuning range of the VCO combined with the frequency divider at 300GHz. Finally, a frequency lock detector is presented for sub-sampling PLL’s that avoids high-frequency dividers, and results in significantly lower power consumption at mm-wave frequencies. Applying these ideas, we demonstrate record breaking VCO’s and frequency synthesizers operating at 40, 200, and 300GHz.

Thanks to the tremendous advances and success of deep neural networks (DNNs), computer architecture research has been booming and enjoying its "Golden Age" recently: a lot of architectural proposals have been proposed for the accelerated execution of the inference or training of DNNs, especially at the edge. Most of them have common architectural features: i.e., hardware-oriented, reconfigurable, domain-specific, and in/near-memory. This talk will try to provide insights on why they are happening and what are the recent findings by showcasing recent research activities mostly in my group.

Neural interface technologies stand to revolutionize disease care for patients with neurological conditions and in the future, the human experience. Today, implantable neurostimulation devices have seen widespread adoption in the treatment of Parkinson’s disease, OCD, epilepsy, and more. Clinical neurostimulators have few channels and provide simple electrical pulses that are programmed by a doctor in a process that can take months or even years. In this talk I will present WAND: Wireless, Artifact-free Neuromodulation Device, which combines high channel count neural recording with stimulation in a truly closed-loop manner for the first time. This technology, enabled by advances in integrated circuit design, will enable patient-specific therapies that will result in improved outcomes and reduced side effects and pave a path to bidirectional brain-machine interfacing. I will also present recent research in a new class of ultrasound-powered interfaces that has enabled us to scale complete wireless neurosensing and neurostimulation devices to volumes below 1mm³, enabling minimally invasive implantation and safe, chronic use inside the human body.

IC chips are key enablers of densely networked smart society and need to be more compliant to security and safety. The talk will start from Electromagnetic Compatibility (EMC) techniques of IC chips on the safety side, toward EMC aware design, analysis and implementation. Then, the challenges will be discussed about the deployment of EMC techniques in the design of IC chips for the higher level of hardware security. Design and simulation techniques of crypto-based secure IC chips with countermeasures for side-channel attacks will also be discussed.

Interactions of IC chips and packaging structures differentiate the electronic performance of power delivery networks (PDNs) in traditional 2D and advanced 2.5D and 3D technologies. This presentation discusses their impacts on signal integrity (SI), power integrity (PI), electromagnetic compatibility (EMC) and electrostatic discharge protection (ESD), through in-depth Si experiments with in-place noise measurements and full-chip level noise simulations. Test vehicles under study are given in traditional 2D face up and flip chip packaging, 2.5D fan-out wafer level packaging (FOWLP), and 3D chip stacking with through silicon vias (TSVs).

Hardware security, application of modern digital cryptography and authentication technologies for protecting information in electronics, involves analog functionality to avoid physical threats in operation fields. This presentation provides an overview with historical aspects of on-chip physical attack protection circuits and assembly structures for the detection and disablement of malicious attempts on cryptographic devices. Design examples to combat passive and active side channel attacks as well as hardware Trojans are discussed and demonstrated with test vehicles.

Noise coupling in RF system-on-chip integration is studied by on-chip and on-board measurements as well as by concatenated simulations at chip and system levels. Integrated power and substrate noise simulation techniques use chip-package-system board combined circuit models and verify noise coupling in mixed analog-digital integration. Wireless system level simulation evaluates the impacts of coupled RF noises on wireless performance through metrics of throughput and error vector magnitude (EVM). In addition, post-silicon techniques at packaging and assembly stages are potential options to mitigate RF noise coupling problems. The presentation will also include demonstrations with test vehicles.

We have developed a CMOS image sensor with an organic photoconductive film (OPF) laminated on pixel circuits, different from those of a conventional silicon image sensors, in which the organic thin film for photoelectric conversion and the charge storage part for signal charge accumulation are completely independent. In this presentation, we focus on the advantageous features of the OPF image sensor; [1] technology that realizes over 120 dB simultaneous-capture wide dynamic range; [2] global shutter technology achieving high saturation signals per unit square that is 10 dB higher than that of silicon image sensors with the global shutter function, without sacrificing pixel area; [3] RGB-NIR sensor technology capable of controlling NIR sensitivity by simply controlling the voltage applied to the OPF. Moreover, we introduce about 8K4K high resolution sensor technologies with 60fps high frame rate, 450ke- high saturation signals, and the global shutter function at the same time. We believe these features of the OPF image sensor will contribute to leaps in the imaging and sensing fields.

System behavior and performance of power management strongly depend on the implementation on circuit level. This tutorial covers the design of DCDC converter building blocks like power switches, gate drivers and their supply, level shifters, error amplifier as well as control loop and current sensing techniques. Circuits for diagnostics and protection will also be addressed. Increasing switching frequency scales down passive components, but poses a challenge for the design of timing critical circuits. The lecture will highlight trade-offs between speed, efficiency, complexity, voltage and current capabilities, etc.

Efficient conversion of energy is one of the megatrends, enabled by advanced semiconductors and microelectronics. As a wide-band gap material, GaN (gallium nitride) offers a huge potential to reduce the overall power electronics system size and cost. However, parameters such as common-mode transient immunity (CMTI) and minimum parasitic gate loop inductance become more challenging, as they degrade the fast-switching performance. This lecture presents design aspects on system and circuit level related to GaN. The concept of high-voltage energy storing (HVES) enables highly integrated gate driver designs, which can even utilize the parasitic gate loop inductance for a resonant gate drive approach. Monolithic GaN-on-Si integration reduces the gate loop inductance nearly to zero and allows for integration of a full power converter including a fully integrated control loop on a single die. A self-supplied 400V 15W offline buck converter GaN-IC will be discussed with which achieves superior efficiency and power density along with lowest component count. Original analog circuits in GaN are presented such as nmos-only auto-zero comparator and high voltage supply regulator.

Power Management has significant impact on the overall system size and cost of systems-on-chip. Multi-MHz DCDC converters enable highly integrated power management solutions. Automotive and server applications are supplied by nominally 12V with a trend for higher supply voltages towards 48V. Hence, converters with high conversion ratio are required to supply CPUs, MCUs, RAM, etc. This talk addresses the challenges on system and circuit design level for highly integrated, fast switching point-of-load converters, including power stage design, high resolution dead time control and soft-switching.

Power management comprises integrated circuits for highly efficient power supplies and for controlling power switches. These have recently gained tremendous importance in order to make electronic solutions for global growth areas such as renewable energies, autonomous driving and biomedical more compact, more energy-efficient and more reliable. Future applications in the field of machine learning and AI will only be possible with intelligent power management to supply complex processors and sensors. This talk gives an overview at system and circuit level of current and future challenges, along with examples including the topics of automotive, wearables, GaN, and current measurement.