Distinguished Lecturer Roster

Digitally assisted ADCs have become mainstream. The move to finer geometry processes and the insatiable need for higher resolution ADCs at higher sample rates have made digital assistance a necessity. In this talk, we discuss some of the advanced calibration techniques for high speed and high resolution ADCs. These include techniques to correct for inter-stage gain errors, non-linearity, settling and memory errors. Techniques covered include correlation-based calibration, summing node calibration, split-ADC calibration, reference ADC calibration and statistical-based techniques. The talk will discuss the advantages and limitations of the different approaches, some of the practical considerations and some state-of-the-art and implementation examples.

Pipelined ADCs with their various incarnations continue to occupy a sweet spot in the high-speed and high-performance ADC space. In this session, we cover the fundamentals of pipelined ADCs from the architecture and circuit perspectives. Architecture trade-offs, and key circuit building blocks will be covered.  

For an ADC designer or user, it is imperative to understand the various performance metrics, and their relationship to each other. Since there are multiple dimensions of performance, the characterization of an A/D converter can be a complicated and confusing process. In this talk, we discuss the metrics used to characterize the A/D converter’s performance, their relation to each other, and the manifestations of the various ADC non-idealities.  

Despite the many applications that could substantially benefit from the energy-performance achievable with an SoC implemented in an advanced process technology, the high costs of designing and verifying such an SoC using current methodologies limits their adoption to end markets greater than ~$1B in size. Not only has this prevented substantial hardware innovation in emerging markets, but even in markets large enough to bear the high initial design cost, designers are being put under constant pressure to improve their productivity given increasingly tight time-to-market constraints and product cycles. In this talk, I will describe a collaborative effort to develop an "agile" approach that aims to substantially reduce the design and verification costs of such advanced SoCs. Building on principles originally developed for agile software design, the key missing piece for hardware is that rather than focusing on developing instances, designers should focus on developing generators that facilitate re-use and enable agile validation as well as verification. As I will describe in this talk, to support this shift in approach, our team is developing technologies that enable generation of digital and analog hardware as well as the means to verify the hardware that is produced. After briefly describing each of these technologies and highlighting some of their key features, I will then briefly describe the SoC generator we have developed and used to tape-out multiple SoC demonstrators on TSMC's 16nm FFC process.

In nearly all modern computational applications, the achievable performance is intimately linked to the cost and speed of communication between chips within the system.  For this reason, link data-rates have continued to scale at an aggressive rate (roughly doubling every 4 years), but since the power available for the I/O circuitry tends to remain relatively constant, the energy-efficiency of the transceivers must simultaneously be improved as well.  Although there has been a push to adopt higher-order modulation schemes (PAM4) and ADC-based solutions at the 56Gb/s generation, these techniques typically result in higher power budgets and/or high latency (due to the use of error correcting codes).  In order to explore the ultimate efficiency limits, my group has therefore focused on mixed-signal NRZ solutions, and in this talk I will describe the circuit and link architecture optimizations that allowed us to realize a complete 60Gb/s transceiver supporting communication over a 0.7m twin-ax cable (~21dB loss at 30GHz) while dissipating only 288mW in a 65nm CMOS process.     

Current and future hardware products are strongly driven by their interfaces (both in terms of sensing/actuation as well as communications), and since all such interfaces must deal with the analog nature of the real world, these products must typically integrate substantial analog functionality. However, the level of analog designer productivity has not really improved along with silicon technology scaling, and for modern processes in particular, have perhaps even taken a step backwards due to dramatic changes in the physical layout design rules. Therefore, if we are to have any chance of addressing the NRE barrier to custom hardware design, we must also address the analog design productivity gap. In this talk I will present our efforts that aim to close this gap by injecting ideas inspired by agile software devleopment into the analog design paradigm. In particular, we have developed an open-source framework called the Berkeley Analog Generator (BAG) that enables analog designers to codify their design approach (i.e., the steps they took to convert a set of inputs specifications into a fabricate-able design) in an executable generator. In this paradigm, rather than delivering a particular instance (i.e., a point design with a given set of specs), analog designers should focus their efforts on the development of these generators. We have successfully practiced this approach on a variety of technologies and analog blocks, and the results from those endeavors will be highlighted throughout the talk.

Systems-on-Chip (SoCs) have been a reality in the past 15 years. Several dozens of Different Functional blocks are being integrated on a single die, reaching transistor counts of over a billion. From the Analog portion of an SoC the Data Converters are probably the most challenging blocks, often limiting system performance and dominating power dissipation. However, requirements regarding yield, die-size, scalability, noise immunity, power and the fact That logic is almost for free, cause distinct differences between embedded Data Converters and their stand-alone, usually general purpose, counterparts. The presentation describes these differences and provides an overview of the state-of-the-art in embedded Data Conversion.

In large SoC’s Data Converters take a dominant position both from a performance Point of view as well as from an energy consumption point of view. The past two decades have shown a strongly intensified search for more power efficient Data Converters, in particular power efficient Analog-to-Digital converters. This presentation will focus on power efficiency of Nyquist-rate Analog to Digital converters and discuss what has been proposed in open literature to reduce the energy consumption, both from a circuit point of view as well as from an architectural point of view. To get a good grasp of how circuit and architectural choices affect the power consumption, a method will be introduced that allows a quick estimation of the power consumption of an ADC, based on the required SNDR, the sampling frequency, the used technology as well as the chosen ADC architecture and circuit implementations. The proposed method enables a comparison based on these choices and can show what their impact is on the power efficiency, without going through the elaborate design of several architectures. It also shows which recent inventions made a large impact on power efficiency and how these inventions can also be of use in other architectures than the ones they have been introduced in.

Introduction to high-speed current-steering DACs. The principle of current-steering DACs is extremely simple and a good designer needs to know all error mechanisms. Common error mechanisms will be discussed, with error sources affecting amplitude, timing or the shape of the basic output pulse. The problem of code-dependent output impedance is discussed, including solutions. A state-of-the-art DAC design will be shown, including measurements and comparisons to theory and literature.

A comprehensive method for power estimation of residue amplifiers is presented. Using this method a definition of power efficiency is given, which subsequently is used to analyze recently published, highly efficient residue amplifiers. Design parameters are identified which have a key influence on the power efficiency and design choices based on power efficiency are discussed. It is shown that the most power efficient residue amplifier topologies share the same core circuit and differ primarily in how this core-circuit is driven from the input. Finally, an overview is given of these topologies, ranked on power efficiency.

Instrumentation applications, such as transducer readouts and smart sensors, require precision analog-to-digital converters (ADCs) with high absolute accuracy and linearity as well as high resolution. Such ADCs often result in poor energy-efficiency and high power consumption, thus making them unsuitable for the use in battery-powered autonomous systems. In this tutorial, it covers the design of energy-efficient high-resolution ADCs for sensor interfaces, which include both architectural- and circuit- level techniques to maintain the energy-efficiency. It also describes practical design aspects from several design examples.

The continuous feature size scaling in CMOS technology has enabled the system to decrease power consumption and lower costs while increasing reliability. The design of low-voltage opamp often poses significant challenges in the scaled CMOS technology. Dynamic amplifiers based on CMOS inverters attracts again and have become a necessity to minimize power consumption in all analog circuit blocks. This tutorial covers the design of energy-efficient inverter-based amplifiers, which includes recent advances to maintain the performance of analog circuitry. It also presents design examples of some state-of-the-art inverter-based amplifiers. 

This talk will discuss the most advanced techniques to achieve high spectral purity and low spur content in digital PLLs. Spur generation induced by nonlinear phase detection will be reviewed, as well as techniques aiming to mitigate nonlinearity of time-to-digital converters. The extension of digital bang-bang PLLs to fractional-N synthesis via the introduction of a digital-to-time converter and its linearity improvement techniques will be reviewed and analyzed.

This tutorial will introduce the fundamentals of analysis and practical implementation of digital PLLs. Unlike analog loops, the design of digital PLLs should take into account quantization, which can potentially generate limit cycles and degrade the output spectrum. A full design flow to meet bandwidth and jitter specifications, avoiding limit cycles, will be illustrated, and a comparison between digital PLLs based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors, will be shown.

Injection-locked phase-locked loops and multiplying delay-locked loops are the two main architectures of frequency synthesisers relaxing the trade-off between jitter and power consumption. This tutorial will first discuss jitter accumulation in realigned oscillators, from a theoretical point of view, and then show how lock range and output spectrum of realigned oscillators are linked to the so-called phase response curve. Finally, the realignment techniques will be extended to the case of fractional-N frequency synthesis and a practical design example of fractional-N multiplying DLL in CMOS will be illustrated.

A phase locked loop can enable the direct frequency- or phase-modulation of the carrier from a digital word, in a variety of different contexts, from polar RF transmitters to chirp generators for FMCW radars. This talk will review the main architectures allowing for wideband FM modulation and tight linearity, such as the two-point injection technique and the digital pre-distortion of the oscillator. Finally, the practical CMOS implementations of a 3.6-GHz phase modulator capable of GMSK/QPSK modulations, and a 20-GHz chirp generator for radar applications will be illustrated.

This talk introduces recent advancement of CMOS image sensors for biomedical applications. The fundamental operation principle is mentioned and then some recent topics on high performance characteristics are presented in terms of biomedical applications. Finally, biomedical applications with CMOS image sensor technology are demonstrated such as retinal prosthesis, fluorescence detection for ELISA, and implantable micro imaging devices.

Recently, combination of genetic engineering and optical technology enables to measure and control biological functions with light. Fluorescent protein such as GFP can be used as an optical tag of a specific molecule, and photoactive protein such as ChR2 can be applied for optical manipulation of biological functions.

This presentation introduces some kinds of implantable optical devices for measuring and controlling biological functions in the brain of a freely-moving rodent. Future direction is addressed for achieving bidirectional optical communication with brain.

Retinal prosthesis is a medical device that can partially restore visual sensation. In this talk, general introduction and present status of retinal prosthesis are presented. Then, issues to achieve a large number of stimulus electrodes are discussed in terms of circuit technology. 

Implantable medical devices (IMD) are nowadays widely employed to restore functions to the impaired individuals suffering from diseases like deafness, blindness, cardiac insufficiency,  incontinence, neural disorders, and many more. Such implantable systems become increasingly challenging, if a large number of sensing or stimulating sites needs to be realized - space and power budget, safety issues, high bidirectional data rates, as well as the vast number of electrical interfaces make the electronic circuit design a complex task of research and development.

This talk will highlight some of the recent worldwide advances towards the realization of high channel count implantable neural interfaces, covering applications and system examples such as the retinal implant and neural modulators with high efficiency frontends, as well as give an overview of the supporting circuitry, such as transcutaneous data telemetry including safety and security aspects, power telemetry, and adaptive power management. 

Continuous-time sigma-delta ADCs have obtained a dominant position for the digitization in wireless receivers. With steadily improved theoretical understanding, architectural innovations and excellent circuit designs, they have achieved bandwidths in the range of hundreds of MHz, while showing high resolution with unbeaten power efficiency. But there is more to it: continuous-time sigma-delta ADCs feature an implicit filtering, which becomes very attractive in the case of blocker or interferer scenarios, which is the usual case in wireless receivers. More recently, there have been a number of architectural and circuit innovations, which improved the robustness of the continuous-time sigma-delta ADC to such interferers, which are known as filtering ADCs. This talk covers different aspects of such continuous-time Σ∆ modulators: 

• Basic Operation and Architectures


• Influence of non-idealities and correction techniques


• Implicit anti-aliasing and signal-filtering


• Robustness to interferers- The filtering ADC


• State of the art Implementations

Power and data telemetry are mandatory components for all implantable systems. Especially multichannel recorders and stimulators require both large power and high data rates. Nonetheless, in many systems the telemetry is just implemented with a holistic approach, but not analyzed in large detail. Based on the fact that most implantable devices dissipate the largest amount of power in the telemetry subsystem, a careful design or even active adapt- ability of the link are thought necessary in order to provide high energy-efficiency as well as to meet with regulatory compliance. Still today, most systems use RF data telemetry and suffer from large power consumption. Power delivery is mostly done without feedback con- trol, or batteries are employed. On the emerging side, power efficient data transfer using UWB or non-RF telemetry, such as optical or ultrasonic approaches have shown to be excellent al- ternatives. Feedback controlled power telemetry or energy harvesting systems have shown high efficiency. This tutorial will give an overview and design guidelines for high-efficiency data and power telemetry for implantable systems. It first reviews the common RF based ap- proaches, and secondly highlights new approaches such as energy harvesting and non-RF communication.

Analog-digital converters are a dominant centerpiece of the digital revolution. Ever higher sampling frequencies and resolutions have to be achieved with increasingly better efficiency, thus lower power and area consumption. In this talk, the achievements in ADC designs over the last decades are shortly reviewed with a focus on what drove those advances, and what boundaries might impact future improvements. This is followed by a closer look to the frontline of the state-of-the-art, where the most recent circuit and system designs for SAR, sigma-delta, pipeline and hybrid ADCs are reviewed and explained.

Wideband millimeter-wave applications including wireless backhaul, WLAN, 5G cellular communication, and radar sensors require wide-tuning, fine-resolution frequency synthesizers with low phase noise and spurs. Although fractional-N digital PLL’s (DPLL) have been demonstrated to be advantageous over their analog counterparts at low GHz frequencies, analog PLL’s currently are predominant at millimeter-wave. Millimeter-wave DPLL’s are rare due to unsolved challenges in the digital phase extraction path that limit the achievable resolution, linearity, power consumption, and operating frequency.

In this talk, we will describe recent advances in the design of millimeter-wave DPLL's and their constituent blocks including inductor-less dividers, high-frequency time-to-digital converters, fine-resolution digitally controlled oscillators etc. We will also describe the extensive use of digital assistance schemes used in these blocks and also at the ADPLL subsystem level that are necessary to meet performance targets reliably in the face of PVT variations and mismatches.

Directional communication using antenna arrays will be a centerpiece of future communication systems in the sub-6 GHz bands and in the millimeter-wave bands. Currently, highly integrated phased-array transceivers are emerging that support steering the main lobe of the antenna array pattern, thereby improving the link budget and providing some spatial filtering. However, in order to increase data rates, network capacity and achieve better interference management, advanced multi-antenna techniques are deemed essential in future wireless networks. These techniques include various forms of multiple-input-multiple-output (MIMO) signaling, adaptive null-steering, spatial equalization, interference mitigation etc. This talk will present recent advances in the design of advanced beamforming transceivers that can support such multi-antenna signal processing. In particular, the design of phased arrays that can address very wide swaths of millimeter-wave spectrum, and the design of hybrid beamformers that can support millimeter-wave MIMO communication will be described.

With the burgeoning number of wireless standards occupying increasingly scarce spectrum, there is an urgent need to develop agile, wideband, interference-robust transceivers. The long-sought goal of such a “universally software reconfigurable” radio remains unfulfilled due to the lack of a CMOS-compatible RF switch of sufficiently high quality. Recently, a new class of reconfigurable RF circuits has emerged based on a new CMOS-compatible RF switch that uses “phase-change (PC)” materials. These materials can be reversibly transformed between low and high resistance states, have low parasitic capacitance. PC-based RF switches can therefore serve as a “more-than-Moore” element that can augment the capabilities of standard CMOS since they can be fabricated in the back-end of line of such technologies.

This talk describes recent advances in RF circuit reconfiguration using PC switches. A background into material choices and switch design considerations is provided, and is followed by a description of the design, fabrication and characterization of several CMOS+PC demonstration circuits that showcase this approach for RF reconfiguration. 

Smart sensors are complex systems comprising a sensor and its interface electronics, used to measure a physical parameter, such as temperature, humidity, pressure, acceleration,…, and converting the reading into the digital domain. Although often neglected, a reference is always required for any measurements, since measuring basically involves comparing the physical parameter of interest to a known quantity. Consequently, references are a fundamental components in any smart sensor, which can even limit the performance of the whole system if not properly designed. In this lecture, an overview of references for smart sensors will be given with specific focus on references that can be implemented on chip in a standard CMOS process. An overview of references available in CMOS will be presented, including resistance, capacitive, voltage, current and frequency references. We will discuss the need for references in smart sensors and their requirements, and explore through practical examples and case studies how the performance of integrated references can meet those requirements .

Nodes for the Internet-of-Things (IoT) need radios that are small, cheap and energy efficient. Frequency references are required for those radios to select the right band for wireless communication. Moreover, a frequency reference enables time synchronization between the nodes in the IoT network, which allows to turn off the radio when transmission or reception are not expected, thus resulting in power saving. Highly accurate frequency references can be implemented using quartz crystals but since such external components would limit the miniaturization of IoT nodes, fully integrated alternatives must be adopted. In addition, such references must guarantee the required accuracy over the wide temperature range expected in several IoT applications and over the supply voltage variations caused by the energy scavengers or the batteries powering the IoT node.

This talk will present the requirements for such fully integrated frequency references and review several alternatives for their implementation. The main sources of inaccuracy and the techniques to minimize their effect will be analyzed, with particular emphasis on supply sensitivity and temperature compensation.

Quantum computers hold the promise to change our everyday lives in this century in the same radical way as the classical computer did in the last century, by efficiently solving problems that are intractable today, such as large number factorization and simulation of quantum systems. Quantum processors must be cooled at cryogenic temperatures well below 1 K and each of their quantum bits (qubit) must be controlled by a classical electronic interface. Since future quantum processors with practical applications will require up to thousands or millions of quantum bits (qubit), the electronic controller must operate at cryogen­ic temperatures as close as possible to the quantum processor, to avoid the unpractical requirement of thousands of cables from the cryogenic refrigerator to a room-temperature controller. This talk will address how standard CMOS technology can be used to build such cryogenic electronic controller.
A brief introduction to quantum computers and their operation will be given, followed by a description of their hardware implementation and their requirements in terms of electronic control and read-out. We will address the challenges of building a scalable silicon-based cryogenic electronic controller, focusing on to use standard CMOS technology to build complex analog, mixed-signal and digital systems and circuits operating down to 4 K and below.

Jitter refers to deviation from ideal timing in clock and data transitions. In wireline communications, jitter reduces the timing margin available for clock and data recovery (CDR) circuits and poses significant challenges to signal integrity as the data rates march towards 64Gb/s/lane and beyond. In this talk, we first review the basic definitions of jitter and its properties, and the effects of jitter on CDR and other building blocks of a wireline system. We then describe the methods of characterizing, modeling, and simulating jitter. Finally, we present some recent works on jitter measurement and jitter mitigation techniques that are used to optimize the link performance.

This talk includes a selection of topics from Circuit Intuitions articles as the have appeared in the SSCS Magazine. The main audience for this talk would be upper-year undergraduate students but may also serve the interest of graduate students and practicing engineers. SSCS Chapter Chairs may request a select subset of Circuit Intuitions articles to be included in this talk.

There have been constant efforts to develop digital-intensive implementation of analog building blocks. The phase-locked loop (PLL), as a key analog block, has been one of the most actively researched topics in this area. The time-to-digital converter (TDC) plays a major role in determination of the achievable performance of digital PLL, and the requirements on TDC becomes even worse in fractional-N PLL. This presentation reviews principles of digital PLL with noise and jitter analyses. The talk also introduces implementation examples of recently proposed synthesizable fractional-N PLLs.

The on-chip oscillator has been widely adopted as a low-cost generator of timing reference for overall system. The requirements of the oscillators have been in the frequency stability, phase noise and power consumption. This presentation reviews basics of RC oscillator and introduces various approaches to overcome trade-off limitation between power consumption and immunity to process, supply, and temperature variations.

With the emergence of wearable and implantable technologies, there has been strong demand on the development of circuit techniques for ultra-low-power consumption while keeping traditional requirements of stable performance. The reference generator is an essential circuit block for supplying internal biases. This talk presents principles and issues in the design of nano-watt and sub-nano-watt implementations of CMOS and bandgap reference generators.

With many chip designs becoming more complex, and with time-to-market a key differentiation, leveraging IP is one compelling approach for chip development teams to gain a competitive edge. However, analog IP re-use has lagged behind digital IP due to challenges in customization, integration, and verification. The complex organizational relationships both within a company and between companies further complicate the IP ecosystem. This talk presents a high-level view of analog IP development and re-use, and uses conceived examples to illustrate some of the benefits and pitfalls of analog IP while gently challenging traditional notions of what it means to be an analog IC designer.

Compared to circuits utilizing voltage or current to convey analog signals, time-based circuits offer unique attributes, ranging from simple, area efficient quantization to more complex techniques for time-based processing such as integration, interpolation, and noise shaping. Although time-based circuits are not new, the availability of fast, low-power transistors in advanced process nodes, combined with the challenges of traditional analog design techniques, has renewed interest in time as a signal domain both in academia and in industry. This talk will look at some obvious and more subtle differences between voltage and time-based circuits, and discuss tradeoffs in the context of application requirements. A few advanced state-of-the-art time-based circuits will motivate the audience to consider how time-based circuits can be a useful tool for their own designs.

Time-based circuits have seen an increased use in advanced process nodes with fast transistors and low supply voltages. Specifically, high-performance ADC see benefits using time-based circuits due to the ease of quantizing binary time-based signals with simple digital circuits. This talk will discuss concepts such as phase-domain signals, noise-shaping, and metastability of time-based quantizers, highlighting a number of ADC architectures that directly utilize time. Finally, recent examples of state-of-the art time-based ADC will be reviewed.
 

This talk will describe methods to enable energy-efficient processing for deep learning, specifically convolutional neural networks (CNN), which is the cornerstone of many deep-learning algorithms. Deep learning plays a critical role in extracting meaningful information out of the zetabytes of sensor data collected every day. For some applications, the goal is to analyze and understand the data to identify trends (e.g., surveillance, portable/wearable electronics); in other applications, the goal is to take immediate action based the data (e.g., robotics/drones, self-driving cars, smart Internet of Things). For many of these applications, local embedded processing near the sensor is preferred over the cloud due to privacy or latency concerns, or limitations in the communication bandwidth. However, at the sensor there are often stringent constraints on energy consumption and cost in addition to throughput and accuracy requirements. Furthermore, flexibility is often required such that the processing can be adapted for different applications or environments (e.g., update the weights and model in the classifier). We will give a short overview of the key concepts in CNNs, discuss its challenges particularly in the embedded space, and highlight various opportunities that can help to address these challenges at various levels of design ranging from architecture, implementation-friendly algorithms, and advanced technologies (including memories and sensors).

Edge computing near the sensor is preferred over the cloud due to privacy or latency concerns for a wide range of applications including robotics/drones, self-driving cars, smart Internet of Things, and portable/wearable electronics.  However, at the sensor there are often stringent constraints on energy consumption and cost in addition to throughput and accuracy requirements. In this talk, we will describe how joint algorithm and hardware design can be used to reduce energy consumption while delivering real-time and robust performance for applications including deep learning, computer vision, autonomous navigation and video/image processing.  We will show how energy-efficient techniques that exploit correlation and sparsity to reduce compute, data movement and storage costs can be applied to various AI tasks including object detection, image classification, depth estimation, super-resolution, localization and mapping.  

Nowadays, the hearing aid technology is facing a new horizon based on advanced digital signal processing, wireless communication and artificial intelligence. In this lecture, new methodology with a systematic solution covering both the auditory periphery and the cognitive system is given. The up to date and rapidly evolves technologies for the binaural hearing aid system are well addressed. The multi-channel wide dynamic range compression, active noise reduction, self-adaptable directivity, acoustic scene analysis, and the wireless linking with other audio or communication systems are presented. The key technologies including the ultra-low power chip design, the advanced digital signal processing (DSP), and the wireless system integration and connectivity are discussed. The micromechanics and high performance electro-acoustics, the miniaturized antenna, the user interface, and the fitting system development are also the important aspects for the hearing aid technologies are shown in this lecture. A smart binaural hearing aid technology, which simultaneously processes the acoustic signals from the four microphones in both ears are indicated which utilizing the computing power from the smart phone to finish the advanced binaural DSP algorithms.

The demand of medical electronic devices, to make the medical devices smaller and smarter, is one of the driving force of integrated circuits and systems. The implantable medical devices (IMD’s), which are fully or partially implanted in the human bodies through surgeries, have a series of strict technical requirements including the choice of frequency and bandwidth, low power consumption, data rate, signal modulation method, disturbing and interference etc. This lecture focuses on a recently proposed technique in the art of radio transceiver design to reduce  power consumption and area occupation. A set of miniature IMD’s have been implemented using this ultra-low power transceiver which can be integrated in different application specific systems-on-a-chip (SoC’s).

To implant electronic systems into the human body  to perform sensing or stimulation in a minimally invasive manner has led to numerous medical advances. Progress in semiconductor technology has paved the way for making the implantable devices increasingly smarter and smaller, but the miniaturization of the power supply remains challenging. In order to power miniaturized implantable medical devices, wireless power transfer (WPT) is desirable. In the WPT system, improving the energy efficiency is a very important objective. The energy transfer efficiency should be as high as possible even with large variations of the coupling and loading conditions. In this lecture, the critical techniques for energy efficiency improvement are addressed. The methodologies include tracking the maximum efficiency point with a low-cost method, optimizing the efficiency of rectifiers and inverters, implementing the power control loop between the transceiver and receiver, increasing the quality factor (Q) of loop antenna coils and the coupling coefficient (k) between coils, and so on. Some systems level implementations of the WPT for popular bio-medical applications, such as involve Gastric Electric Stimulator (GES), Hearing Aid System, and digestive Tract Endoscopy System, are also presented in the lecture. A variety of special issues for these implementations have been discussed.

With 5G communication just around the corner, there is a rapidly increasing need for high-performance mm-Wave power amplifiers. However, these next-generation mm-Wave PAs are often expected to deliver nearly “perfect” performance. They should offer large output power to ensure sufficient link budget, broad bandwidth to support multi-standard communication or frequency reconfigurability/agility, high peak and back-off efficiency for energy saving, and also inherent linearity for Gbit/s complex modulations with minimum or even no digital pre-distortions (DPD). It is noteworthy that in conventional design notions a given PA design should typically take trade-offs among these performance aspects, instead of trying to achieve all of them. Interestingly, this somehow unreasonable quest for “perfect” mm-Wave PAs has recently stimulated a new wave of mm-Wave PA innovations at both circuit levels and architecture levels, which have substantially advanced the state of the art.

In this talk, we will review several recent mm-Wave PA designs that feature various design techniques and innovations at both circuit-level (nonlinearity compensation, continuous-mode operations, broadband harmonic tuning) and architecture-level (such as Doherty and outphasing PAs). We will also showcase several mm-Wave PA/antenna co-design examples that exploit new antenna structures as a new design paradigm to further enhance mm-Wave PA output power and efficiency.

Conventionally, antennas and electronic designs are often treated as two distinct and separated domains: antenna designers handle the antennas; circuit designers deal with the electronics; and they only talk to each other over one single standard 50ohm interface. It is noteworthy that the far-field antenna radiation characteristics are completely governed by its local current and voltage distributions, suggesting the possibility of using “multiple distributed electronics feeds” to “actively synthesize” desired antenna responses and achieve “element-level antenna reconfigurability.” The multi-feed antenna also can be viewed as a group of electrically small radiators, and the multiple feeds actively couple them together for collective high-performance radiation. Moreover, since on-chip antennas have become ubiquitous at mm-Wave and cost of adding more on-chip circuits are negligible, boundaries of these two domains are further blurred, and thus multi-feed antennas co-integrated with complex electronics now emerge as a very promising technology choice particularly for future mm-Wave massive MIMO systems.

In this talk, we will present several recently reported multi-feed radiators co-integrated with complex transmitter/receiver electronics in silicon to achieve unprecedented mm-Wave front-end performance. On-chip or on-package multi-feed antennas can support low-loss on-antenna power combining and radiation impedance down-scaling in one single antenna footprint, radically pushing the limit of output power and efficiency for mm-Wave transmitters in silicon. The multi-feed antennas also enable on-antenna active load modulation, achieving high-efficiency on-antenna Doherty or Outphasing silicon-based transmitters with state-of-the-art energy efficiency. Furthermore, inherently wideband feed isolation can be explored in multi-feed antennas to realize world-first mm-Wave full-duplex chip-to-chip communication link with Gbit/s 64QAM signals.

Living cells are highly complex systems that often exhibit multi-physics responses under external stimulus. Holistic cellular characterizations necessitates interface technologies that offer (1) single-cell resolution, (2) multi-modality interfacing with cells, (3) real-time two-way communication (sensing and actuation), (4) compatibility with high throughput massively parallel operations, and (5) possibility of production at commercial quantities. The nanometer-scale complementary metal-oxide semiconductor (CMOS) process is a potential candidate to realize cell-microelectronics interfaces. Electronics-based computations and signal processing, such as machine learning methods, may drastically relax the requirement on the physical interface and lead to further pixel miniaturization.

In this talk, we will present several fully integrated multi-modality CMOS cellular joint sensor/actuator arrays with multiple sensing modalities in every array pixel to characterize different cell physiological responses, including extracellular voltage recording, cellular impedance mapping, and optical detection with shadow imaging and bioluminescence sensing. Each pixel also contains electrical voltage/current excitation for cellular stimulation. These reported CMOS cellular joint sensor/actuator arrays comprise up-to 22k multi-modality pixels on each chip with spatial resolution down to 17um*17um/pixel, achieving single-cell resolution. Multi-modality cellular sensing at the pixel level is supported to enable holistic characterization and concurrent joint-modality physiological monitoring on the same cellular sample. Comprehensive biological experiments with different living cell samples demonstrate the screening functionalities.

Dynamic device, circuit, and system parameter variations degrade processor performance, energy efficiency, and yield across all market segments, ranging from small embedded cores in an Internet of Things (IoT) device to large multicore servers.  This lecture introduces the primary variations during the processor operational lifetime, including supply voltage droops, temperature changes, transistor and interconnect aging, radiation-induced soft errors, and workload fluctuations.  This presentation then describes the negative impact of these variations on processor logic and memory across a wide range of voltage and clock frequency operating conditions.  To mitigate the adverse effects from dynamic variations, this lecture presents adaptive and resilient circuits while highlighting the key design trade-offs and testing implications for product deployment.

Deep neural networks (DNNs) are commonly used in artificial intelligence (AI) processors to achieve high-accuracy recognition and prediction functions for a variety of applications. However, DNN-based AI processors using a conventional (von Neumann) architecture face challenges in long latency and high energy consumption due to memory wall issue in data movement and large-volume computation. Computing-in-memory (CIM) or process-in-memory (PIM) methods have been proposed to improve computational efficiency by enabling parallel computing within the memory macro or array, thereby reducing the instances of memory access and suppressing the volume of intermediate data to be generated. In this talk, I will review recent progress and the challenges in circuit designs of SRAM and emerging memory (STT-MRAM, ReRAM and PCM) based CIMs for AI chips.

Memory has become one of the bottlenecks in the development of IoT and wearable devices with low energy consumption. This seminar addresses trends in the development of on-chip (embedded) nonvolatile memory (NVM) for energy-efficient IoT applications. The first part of this seminar will introduce a variety of nonvolatile memory (NVM) technologies, including eFlash, resistive RAM (ReRAM), phase-change memory (PCM), and STT-MRAM. This seminar will explore the challenges and silicon verified solutions in the design of low-power and high-speed circuits for on-chip NVM macros. The 2nd part of this seminar will explore the implementation of emerging memory beyond conventional memory applications, such as nonvolatile-logics (nvLogics) and nonvolatile processors for frequent-off intelligent IoT chips.

Internet of Things (IoT) devices are rapidly becoming common place in consumer, industrial, medical, automotive applications and elsewhere. In most cases, a network of multiple devices, called nodes, each one including sensors and actuators interfacing to the physical world, communicates wirelessly with a hub/base station, which, in turn, acts as a gateway to internet. This lecture introduces to the analog/mixed-signal hardware of the IoT devices and the hub. It discusses the most common sensors and actuators used in the network nodes, their signal conditioning electronics, the data acquisition/synthesis (ADCs/DACs), and briefly touches upon the embedded digital signal processing. A brief technical introduction makes the core topics accessible to the non-experts. Some case studies illustrating the practical implementations of IoT devices to a variety of applications and real products complement the technology coverage.

Demand for ultra-wideband data acquisition and real time processing systems handling analog signals in the GHz range comes from applications in high performance instrumentation, defense and infrastructure communication systems among others. In these cases, front-end circuitry and ADCs/DACs are rapidly getting integrated together with front-end digital processing, preferably in mixed-signal CMOS systems-on-a-chip. This lecture will briefly review some of the technical challenges faced by analog designers developing such systems along with some the technologies behind that. The performance demands, coupled together with limitations of the underlying technologies such as those of nanometer CMOS processes and die packaging, require a comprehensive design approach combining circuits and architectural innovation with algorithmic techniques. This lecture introduces some of the present engineering approaches being developed to tackle such challenges. 

Many emerging applications in wearable sensors, unattended ground sensor networks, and other Internet-of-Things (IoT) devices measure signals such as human physiochemistry, ambient temperature, or the presence of intruders - all of which are signals that do not tend to vary rapidly with time. In such systems, battery life is often dominated by radios - not because of large payloads, but rather due to the constant communication of small packets in order to maintain network synchronization. This presentation will discuss how wake-up receivers (WuRXs), if designed for bandwidths that support the average expected throughput needs of a given application, can be used to dramatically reduce average power consumption in such applications. Conventional wake-up radio architectures will be reviewed and analyzed for their strengths and weaknesses, followed by detailed discussions on state-of-the-art architecture and circuit techniques that can be used to improve sensitivity and/or reduce WuRX power consumption.

Wearable devices hold considerable promise to diagnose, monitor, and treat various medical conditions and/or track the real-time status of athletes. However, most current generation wearable devices only monitor a limited number of physical and electrophysiological parameters that are, in many cases, only peripherally related to many health conditions or fitness enterprises. Furthermore, many such wearable devices are large, bulky, and rigid, thereby precluding seamless integration into daily life.

Addressing these issues requires:  1) development of new sensor technologies that provide more actionable data in thin, flexible form factors; 2) engineering of supporting electronic infrastructure to condition, digitize, and wirelessly communicate data in an extremely energy efficient manner; and 3) new data analytics to process and understand newly generated data streams. This presentation will discuss emerging sensor technologies that can non-invasively monitor physiochemistry (e.g., glucose, blood alcohol concentration, and lactate) in thin, flexible, and energy-efficiency wearable devices, alongside a brief look at what kind of analytics are necessary to parse and understand this data. We will also cover integrated circuit building blocks and architectures that make acquisition and telemetry of sensed information so energy-efficient that that they can be easily powered from new local energy sources (e.g., wearable glucose biofuel cells). Such net-zero-power operation will ultimately enable devices that are completely autonomous and invisible to the user, to the point where users are virtually unaware of their wearable devices after placement – in other words, they are “unawearable” devices. 

Small, ultra-low-power integrated circuits afford new opportunities to sense and interact with the environment in new and exciting ways – for example by probing brain matter across arbitrary 3D geometries, to sensing temperature, humidity, or chemicals within or around the human body. Over the past several years, our group has demonstrated wireless ion sensing systems than consume less than 10nW of power, wireless glucose sensing systems powered directly by glucose biofuels, single-chip mm-sized neural implants with integrated electrodes, antennas, amplifiers, digitizers, stimulators, and power/telemetry units, and ultra-small and/or ultra-low-power building blocks including reference generators, DC-DC converters, and wake-up radios. This talk will review such contributions, and the challenges and opportunities moving towards self-powered mm-sized electronic systems.

Nowadays use of millimeter-wave spectrum for wireless communication is one of the most important technologies in next generation wireless such as 5G, IEEE802.11ad/ay, IEEE802.15.3d, etc. More than 10Gbps data rate is targeted for satisfying the social demand. This talk will explain basic system-level design of millimeter-wave transceiver as well as modeling and simulation for CMOS technology. Some design examples of millimeter-wave transceivers will be also introduced, which achieves 50Gbps and 120Gbps at 60GHz and 100GHz, respectively. The talk concludes with a discussion on future directions of millimeter-wave wireless communication, based on Shannon and Friis equations.

The wireless communication is one of the key technologies for realizing the future smart society. The conventional omni-directional wireless communication using microwave has been studied so far, and now the directional wireless communication using millimeter-wave (30-300GHz) is opening a new technology field of communication. The directional wireless communication using the millimeter-wave spectrum can accept spatial co-existence and multiplexing as well as use of wide frequency bandwidth. In this presentation, a millimeter-wave CMOS phased-array transceiver design is explained about phased-array architectures, phase shifters, power amplifiers, phase/gain calibration, measurement techniques, etc. The talk concludes with a discussion on future directions of millimeter-wave wireless communication, based on Shannon and Friis equations.

In this presentation, some design techniques for fractional-N digital PLL will be introduced to improve both jitter and power consumption for low-power wireless applications. A highly-linear and low-power DTC and TDC will be presented as well as system-level optimization. An isolated constant-slope DTC realizes 10bit 0.1mW operation with 26MHz reference clock, and sub-ps INL is achieved. The DTC-based AD-PLL achieves FoM of -246dB with 0.98mW power consumption and -56dBc worst-case fractional spur. For further power saving, duty-cycled FLL, sub-sampling/sampling switching, charge-recycling DTC, and transformer-based DCO for impedance peaking will be also explained, which achieves 0.265mw power consumption with FoM of -237dB at 2.4GHz. Finally, a DPLL-based ADC and a BLE transceiver using DPLL will be introduced.

Many IoT devices, especially those with very stringent energy constraints, operate in an intermittent manner. The device wakes up infrequently, performs a burst of activity, and goes back to a sleep/inactive mode. Clocking serves multiple functions in such devices. For example, during the burst of activity, a high frequency stable crystal oscillator may be required for the operation of a wireless transceiver. Alternatively, a low frequency real time clock (RTC) that is always ON may be needed to provide crucial sleep and wakeup timer functionality. As such, overall energy consumption in such IoT devices will remain high unless the clocks themselves consume very little energy. To address this challenge, my group has developed two complementary approaches. The first technique enables rapid startup of high-Q crystal oscillators whereas the second one develops a new low power oscillator sustaining circuit. While the latter reduces the power consumption of always ON oscillators, the former allows the clocks themselves to be aggressively duty cycled along with the other circuitry. This talk will describe both techniques and how they enable low power clocking.

Clever signal processing is capable of effectively resolving many of the challenges in analog, mixed-signal, and RF IC design posed by a variety of factors such as process variability, mismatches, device non-linearity. This approach takes different forms – post-processing of ADCs, pre-processing of DACs, digital pre-distortion of PAs, mismatch shaping, intentional random dithering, calibration etc.,  – invariably exploiting the abundant digital logic capabilities of modern CMOS processes to address the aforementioned errors. We have been developing several such techniques over the years. This talk will illustrate their application to open loop phase modulators which are widely used in wideband polar and IQ modulators, and in frequency synthesis, especially in very fine CMOS processes. Achieving low EVM and/or low spurious content is of great importance to these blocks, but they invariably suffer from device mismatches. The talk will describe an array of signal processing tecniques – dither based signal conditioning, least mean square (LMS) based spur cancellation etc. -  and how they were employed to achieve a sub-100fs fractional frequency synthesizer with spurious tones as low as –100 dBc on a 2.4GHz carrier.

Sharp, programmable, linear, integrated filters are enabling components for software defined and cognitive radio applications. However, they are difficult to realize: SAW and MEMS based filters are sharp and linear but not very programmable; active filters can be sharp and programmable but are not very linear; sampled charge domain filtering is sharp and programmable but the burden of the linearity is on the front end voltage-current converter. My group has developed a unique alternative that purposefully employs periodically time-varying circuit components to realize very sharp, linear, and programmable filters for use in RF front ends. This talk will describe how even simple 1st order RC filters can be converted into very sharp filters just by making one of the components, a resistor, vary periodically with time. The talk will show how our technique goes against conventional wisdom by exploiting sampling aliases rather than struggling to suppress them prior to sampling. It will describe how we applied the technique to realize RF front-ends and spectrum scanners with some of the best reported blocker suppression, linearity, and  power consumption. 

Power electronics can be found in everything from electric vehicles and industrial motors, to laptop power adaptors that hook up to wall outlets. While silicon still dominates the power semiconductor landscape, the recent onset of wide-bandgap semiconductor (WBG) devices promises low loss, higher frequency operation of converters leading to smaller, lighter power supplies. This talk will introduce the properties of high voltage (200-1200V) Si superjunction and WBG devices and discuss their relative merits. The common power converter topologies employed in power systems will be explored along with their associated gate-drive and protection circuits.

Power electronics can be found in everything from cellphones and laptops to gasoline/electric vehicles, industrial motors and inverters that connect solar panels to the electric grid. With close to 80% of electrical energy consumption in the US expected to flow through a power converter by 2030, innovative solutions are required to tackle key issues related to conversion efficiency, power density and cost. This talk will look at the trends in power electronics across different application spaces, describe the ongoing research efforts and highlight the challenges ahead.

With the advent of IoT technology, a wide variety of electronic devices are expected to be deployed in often inaccessible places. Keeping these space-constrained devices powered up for their intended lifetimes is one of the primary concerns in the widespread adoption of this technology. In this talk, I will look at the energy needs of IoT devices, discuss the power delivery architecture and examine the possibility of self-powered operation. The talk will delve into the basics of energy harvesting sources, storage mechanisms (batteries, supercapacitors) and the associated power management circuits needed (low-power DC/DC converters, chargers) to extend the operational lifetime of IoT devices. 

Power Amplifiers are a key component for any communication system. Combining energy efficiency, output power, gain, bandwidth and linearity in one single circuit requires a profound understanding of the different circuit trade-offs, the various system requirements and the technology limitations.

In this presentation, an overview of system requirements and PA architectures will be given, highlighting the strengths and weaknesses of each solution. Power combining and device stacking, being essential techniques to achieve high output power in low-voltage technologies, will be explained in more detail. Guidelines to design broadband and linear PAs will be discussed, complemented with many examples in nanometer CMOS (65nm-28nm) and FD-SOI (22nm). Finally, various circuit techniques to reduce AM/AM and AM/PM distortion in combination with high bandwidth will be discussed in more details and explained with several examples at 28GHz and 77GHz.

Using polymers or plastics as a flexible guided dielectric channel, together with mm-wave signals and Silicon chips, was recently proposed as a complementary alternative to optical and copper. Often referred to as Polymer Microwave Fibers (PMF), the mechanical robustness and EMI tolerance are key differentiators for this communication approach. Compared to optical communication, no EO/OE conversion is needed since the mm-wave signal is directly launched into the fiber with an antenna. Furthermore, the connectors have a much higher robustness compared to optical connectors. Compared to copper wireline, far less EMI issues arise since no metal is being used in the channel.

Several demonstrators have been developed both at Universities and companies, revealing the strengths and weaknesses of this approach. This presentation will give an in-depth discussion of the topic, discuss some of the implementation challenges and will give a good understanding of the benefits and drawback of PMF, and conclude with an outlook of the future of PMF. 

The maximum operating frequency of CMOS has steadily increased over the past thirty years and extrapolations would predict THz circuits in CMOS soon. Compared to other technologies, CMOS does offer integration complexity paving the road for entire THz systems. As such, potential applications such as near-field scanning, quality control, spectroscopy and imaging could be pushed to the consumer market.

However, CMOS scaling also resulted into thinner interconnects with higher intrinsic resistance which in turn limits the maximum operating frequency. On the other hand, one could go beyond the fmax-limit by exploiting the non-linear behavior of a transistor. This concept is used already in frequency-doubler and -triplers and can be extended to entire transmitters and receivers. This talk will highlight some of these challenges when designing circuits in CMOS in the THz (300GHz-3THz) frequency band. Several examples in 40nm and 28nm CMOS at a frequency range from 200 to 620GHz will be discussed.

The ability to allow predictive, proactive, personalized and preventive and participatory healthcare analytics through complex information extraction from bio-molecular level to physiological signal monitoring can have transformative impact in healthcare in future. However, while wearable technologies are maturing with time, extracting bio-molecular information that relies on protein or genetic material is still largely centralized laboratory based. Dominated by optical-based detection technologies, these end-to-end systems are large, bulky and expensive with a complex arrangement of various optical components such as lenses, filters, collimators whose functionalities haven’t changed fundamentally in the last 50 years.

In this talk, I will present approaches that allow elimination of all external optical elements for mm-scale, fully ‘optics-free’ single chip complex optical systems. In an absolutely no-change in CMOS fabrication we will show how integrated metal interconnects in the deep sub-wavelength regime can allow highly scalable and complex nanoplasmonic elements operating in the visible range and integrated in the same substrate as the integrated electronics.  In a series of demonstrative examples ranging from mm-scale, highly multiplexed, pill-sized bio-versatile molecular sensors 100-fM levels of DNA and protein sensitivity to optical spectrometers, I will try to show how this nano-optics/electronics co-design approach opens up a new co-design space across the optical, electronic and signal processing layers. By allowing new system properties that is greater than sum of its parts, this can eventually lead to a new class of intelligent, distributed, low-power sensors for future diagnostics, health monitoring, environmental safety, food and water quality monitoring. 

Future mm-Wave systems are expected to operate in a complex and heterogeneous environment extending from the electromagnetic propagation channels right up to the network layers. As disjointed spectral bands open up across 28-100 GHz for 5G applications and beyond, spectrally agile, robust mmWave front-ends that can allow dynamic reconfiguration in large scale mmWave MIMO arrays can have a transformative impact in spectrum efficiency and deployment of such 5G systems.

While this involves a series of challenges from the antenna to the transceivers I will highlight two specific directions in this talk. These emerge through a multi-port transceiver and multi-port antenna framework that allow each element to assume properties distinct from classical array architectures. Firstly, I will discuss the challenges of enabling a transmitter front-end particularly the power amplifier for such a spectrally-agile mmWave system. I will discuss multiport architectures that can allow simultaneously broadband, high power and high back-off efficient transmitter front-end, properties that typically strongly trade-off with each other. In the next part of the talk, we will discuss how such multi-port transceivers can be co-design and co-integrated with multi-port antennas to allow such spectrally-agile architectures, In addition to extremely high bandwidths, these architectures allow element level programmability needed for multi-band periodic arrays. These include the ability to reject interferers passively directly at the element antenna surface, reconfigure individual antenna patterns, and allow frequency, spatial, pattern and polarization diversity in scalable arrays.

Silicon-based Terahertz systems is a field that is only about a decade old. In this time, we have seen a phenomenal growth of silicon systems operating at THz frequencies for a wide range of applications in sensing, imaging and communication. It can be argued that both the ‘THz gap’ and the ‘technology and applications gap’ is closing in meaningful ways in the THz range. Technologies beyond 100 GHz focusing on sensing, imaging and wireless back-haul links are getting attractive as we enter into a new area of highly dense network of autonomous systems requiring ultra-high speed and reliable links.

In order to move beyond this inflection point as Moore’s law continue to slow, I will discuss why we need to look beyond the classical ‘device’-level metrics of efficiency and sensitivity of THz sources and detectors towards holistic ‘system’ level properties such as scalability and programmability. Such properties are critically important for applications in sensing and imaging, as evidenced across sensor fusion technologies across mmWave, IR and optical frequencies. The ultimate programmability in THz sources and sensors is one that can synthesize or receive THz fields with arbitrary configuration and spectrum. In this talk, I will highlight approaches that cut across electromagnetics, circuits, systems and signal processing, to allow for such reconfigurability in THz signal synthesis and sensing, yet realized with devices that are themselves not very efficient. Incorporating, such programmability across the three field properties of spectrum, beam pattern and polarization, I will comment on what could be the major directions for the field in the coming decade.

A gate driver IC is an important circuit bridging the voltage gap between control ICs operating at less than 5V and the power electronics operating above 100V. The conventional gate driver IC, however, just turns on/off the power transistors and shows the trade-off between the switching loss and the switching noise of the power transistors. In addition, the conventional gate driver IC need to be customized for a large variety of power transistors. To solve the problems, we proposed a programmable general-purpose digital gate driver IC, which dynamically changes the gate drive current during the turn-on/off transient with digital control bits. In the developed gate driver IC fabricated with 40V, 0.18um BCD process, the 6-bit gate control signals with four 160-ns time steps are globally optimized using a simulated annealing algorithm, reducing the switching noise by 37% and the switching loss by 47% at the double pulse test of 300V, 50A insulated gate bipolar transistor (IGBT). The gate driver is also applied to a half-bridge inverter, where the gate driving waveform is changed depending on the load current.

Integrated voltage regulation is critical to the energy efficiency in every systems ranging from high-end processors to ultra-low power IoT devices. Challenges of the integrated power management circuits include the large number of voltage domains, DVFS per domain, large current transients, and wide dynamic range of current loads. In addition, IoT systems present new challenges to the voltage regulators, keeping the high power conversion efficiency at the ultra-low input voltage ( < 0.1V) and/or the ultra-small output current ( < 1uA). In this talk, I will present several circuit designs of voltage regulators for IoT systems, including a sub-0.5V digital LDO / digital-analog hybrid LDO, a sub-0.5V-input buck converter, and a sub-0.1V-input boost converter for the thermoelectric energy harvesting.

The organic electronics enables flexible, large-area, and distributed sensor and/or actuator array and is suitable for the wearing-unconscious devices used in biomedical and healthcare applications.

Power delivery to ultra-thin flexible devices with the thickness of 1um to 10um, however, is a challenge, because wired connections and rigid battery are not allowed. To solve the problem, novel flexible devices for wearable healthcare applications with the energy harvesting or the wireless powering using organic circuits are proposed and demonstrated. In this talk, I will show an insole pedometer with piezoelectric energy harvesters, a fever alarm armband with solar cells, and a wet sensor sheet in a diaper with wireless powering.