IEEE Solid-State Circuits Society

OJ-SSCS Special Issue on High-Performance Frequency Synthesizers

Frequency synthesizers are among the most critical blocks in wireless, wireline, and digital clocking applications. Several advances have been done in recent years bringing the rms integrated jitter of multi-GHz frequency sources below the barrier of 100 fs, and demonstrating direct modulation of phase-locked loops at wide bandwidth. Next generation 5G/6G communication and sensing applications require local oscillators (LOs) with even higher spectral purity, at lower power consumption and higher frequency. Besides that, clock generators at increasingly lower jitter are demanded in wireline and digital applications, as well as in clocking of ultra-high-resolution analog-to-digital converters.

This special issue aims to cover the latest advances in frequency synthesis circuits and systems to efficiently generate LO signals with low phase noise, low spurious tones, and large modulation bandwidth. The issue aims to target designs for high-performance local oscillators in wireless communications, millimeter-wave frequency synthesis, radar systems, low-power sensor networks, wireline applications, and clock generation for data converters and digital systems. Original research contributions describing new integrated circuits and systems are desired, along with in-depth and comprehensive review articles. 

Authors are invited to submit papers following the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) guidelines, within the remit of this Special Section call. Topics include (but are not limited to):

• Frequency synthesizers for wireless communications
• Millimeter-wave frequency synthesizer architectures
• Frequency synthesizers for radar systems
• Low-power frequency synthesis for sensor networks
• Direct phase/frequency modulators
• Phase-locked loops for wireline applications
• Clock generation for digital systems

Submission Guidelines: All submitted manuscripts must

(i)       conform to OJ-SSCS' normal formatting requirements and page count limits;

(ii)      incorporate no less than 70% of new (previously unpublished) material;

(iii)    validate principal claims with experimental results;

(iv)     be submitted online at: https://mc.manuscriptcentral.com/oj-sscs

Please note that you need to select “High-Performance Frequency Synthesizers” when you submit a paper to this Special Issue.

Deadlines

Special Section Open for Submissions: March 1, 2024

Paper Submission Deadline: May 24, 2024

First Notification: July 15, 2024

Revision Submission: August 15, 2024

Final Decision: September 15, 2024

Publication Online: October 15, 2024

Guest Editors

Prof. Salvatore Levantino, Politecnico di Milano, salvatore.levantino@polimi.it

Dr. Wanghua Wu, Samsung Semiconductor, wanghuawu@gmail.com

IEEE SSCS Women in Circuits Rising Stars 2024 Workshop Chair and Vice-Chair

IEEE SSCS Women in Circuits Rising Stars 2024 Workshop Organizing Committee

 Women in Circuits Rising Stars 2024 Workshop Advisory Board

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 

Special Topic on 3D Logic and Memory for Energy Efficient Computing

CALL FOR PAPERS 

Guest Editors

Yu Cao, University of Minnesota, yucao@umn.edu 

Jeff Zhang, Arizona State University, jeffzhang@asu.edu

Editor-in-Chief

Azad Naeemi, Georgia Institute of Technology, azad@gatech.edu 

Aims and Scope 

Monolithic microelectronic design is facing tremendous challenges in the growing need of computation memory bandwidth and latency, and the energy efficiency of computation which is limiting its performance and cost. Although recent advances (e.g., domain-specific acceleration, near-memory and in-memory computing techniques) try to address these issues, the scaling trend of monolithic design still lags behind the ever-increasing demand of AI algorithms, high-performance computing, high-definition sensing and other data-intensive applications. In this context, technological innovations, in particular 3D integration through packaging and monolithic methods, are critical to enabling heterogeneous integration (HI) and bringing significant performance, energy and cost benefits beyond traditional chip design. 3D logic and memory design allow heterogeneous functional macros (i.e. chiplets) to be flexibly produced and connected with higher interconnection density, length reduction and area utilization, opening new opportunities across the microelectronic design stack.

The paradigm shift to heterogeneous integration and monolithic 3D methods requires a tight collaboration between packaging and chiplet designs spanning the entire design cycle, including devices, circuits, architectures, and design automation tools. Logic and memory will be partitioned into various 3D modules. The designers need to customize each module and define the interface, and assess system-level tradeoffs in performance, data movement, and energy efficiency. Design and synthesis tools have to be aware of 3D integration and planning knowledge (e.g., power delivery, heat dissipation and reliability) to enable the packaging and chiplet co-design. Furthermore, early predictive modeling and analysis of the 3D HI circuits and systems are essential to minimize the iteration cost between 3D architecture definition and design implementation.

This special issue of the IEEE Journal on Exploratory Computational Devices and Circuits (JXCDC) aims to call for the recent research advances in the area of 3D logic and memory design spanning from monolithic 3D and advanced packaging technology to circuits and architectures. Papers on co-design and optimization across multiple domains are encouraged.

Topics of Interests

Prospective authors are invited to submit original works and/or extended works based on conference presentations on various aspects of 3D logic and memory design for energy efficient computing. Topics of special interest include but are not limited to:

·       Technology perspectives of 3D heterogeneous integration

·       Emerging monolithic 3D logic and memory devices to improve energy efficiency of computation.

·       Advanced packaging for 2.5D and 3D integration to improve energy efficiency of computation.

·       Logic design and partition for a 3D system

·       Network topology for 3D data movement

·       3D memory design and architectures to reduce the power consumption of data movement.

·       Signaling interface cross 3D modules

·       Thermal cooling and management to address the increased power density of 3D integration.

·       Power delivery, thermal management and reliability of 3D integrated circuits

·       Power delivery, thermal management and reliability of 3D integrated circuits

·       Architectural innovations for energy-efficient 3D HI

·       Prototypes of multi-tier logic and memory macros

·       EDA tools for multi-domain 3D integration

Information on submission guidelines can be found at the JxCDC page on the SSCS website.

Paper submissions must be done through the IEEE Author Portal website: https://ieee.atyponrex.com/journal/JXCDC 

Important Dates  

Open for Submission: February 15th, 2024

Submission Deadline: May 31st, 2024

First Notification: June 30th, 2024

Revision Submission: July 15th, 2024

Final Decision: July 31st, 2024

Publication Online: August 15th, 2024

The IEEE SSCS Women in Circuits, together with ISSCC, is sponsoring the "Rising Stars 2024 Workshop" for outstanding students and young professionals in Electrical Engineering and Computer Science. We will be selecting 24 bright minds from both academia and industry, with a holistic approach to diversity.

The workshop includes a special dinner, distinguished talk from IEEE Fellow Prof. Ingrid Verbauwhede, and a poster session with elevator pitches. Additionally, established members of academia and industry will talk about their unique journeys in a career panel: "Sharing our Paths to Success", touching upon educational choices, research pursuits, skill development, networking, work-life balance, effective transitioning between academia and industry, and more. The panel is open to all ISSCC 2024 attendees and the public.  

Testimonials

APPLICATION INFORMATION

Eligibility

Applicants should be undergraduate, graduate, and young professionals who have graduated within the last two years at the time of the workshop or they must have obtained their last degree no earlier than 2022 and currently do not hold a faculty position. Successful candidates will be required to present pitches and posters at the workshop, with some special exceptions. We will also have pitch rehearsals on Sunday, February 18. All applications must be submitted by October 6, 2023 (11:59 PM PT). 

Required materials:

1. Personal statement that includes research, teaching, and technical topic interests (maximum 2-pages, excluding references, PDF)

2. CV (no page limit, PDF)

3. Contact, personal information, education history, and professional interests (please complete online form)

4. At least one reference who can provide a letter of recommendation. 
   (A recommendation request will be sent when you add your reference to the application system.)

5. Short bio + headshot

6. Diversity statement (maximum 1 page, PDF)

Call for Applications: September 1, 2023

Application Deadline: October 6, 2023 (11:59 PM PT)

Acceptance Notification: November 3, 2023

Rising Stars 2024 Workshop: February 19, 2024 (6:00 PM – 9:30 PM PT)

Rehearsals on February 18, 2024

Accommodations and Travel

The SSCS Women in Circuits will not be able to cover travel and accommodations, however, students may apply for IEEE SSCS Travel Grants below.

Contact Us

Email inquiries can be directed to: sscs-risingstars@ieee.org