Special Topic on Steep Slope Transistors for Energy-Efficient Computing & More

Guest Editor:
Alan Seabaugh,
University of Notre Dame, seabaugh.1@nd.edu

Editor-in-Chief:
Azad Naeemi, Georgia Institute of Technology, azad@gatech.edu

Aims and Scope:

Tunnel field-effect transistors (FETs) and low-subthreshold-swing steep-slope (SS) transistors hold promise to outperform complementary metal-oxide semiconductor technology (CMOS) at low voltage and realize more energy-efficient logic for computation. The aim of this special topics issue is to highlight experimental advances and ideas that make SS transistors attractive for integration with CMOS to realize better power-performance logic. Aspirational characteristics for n- and p-type steep transistors can be summarized as follows: drain currents exceeding 200 mA/mm at a supply voltage below 0.4 V, with SS less than 60 mV/decade beginning near 1 mA/mm and spanning more than 4 decades. Papers describing theory and modeling of transistors which can meet and surpass these goals are of interest, as are papers which assess the full design stack from devices to circuits and architecture to applications to identify system bottlenecks and inform technology development for computing, communications, or other applications. Materials approaches are not restricted to silicon CMOS and can be based on any semiconductor technology and incorporate multiferroic or other performance boosters. New approaches based on three-dimensional integration, heterogeneous integration, processing, or insights from manufacturing are also within the scope of this issue to advance understanding and progress in SS transistors.

Topics of Interest:

TFET and other steep slope transistors with path to outperform CMOS at low voltage

            • Experimental progress

            • Theory and modeling

            • Si, III-V, III-N, two-dimensional semiconductors and heterojunctions

            • Multiferroic and other material/device design approaches

            • 3-D integration, heterogeneous integration, processing, manufacturing

Full-stack design to inform technology development

 

Important Dates:

·         Open for Submission:  June 1st, 2023

·         Submission Deadline: Sept. 1st, 2023 EXTENDED: Sept. 29th, 2023

·         First Notification: Oct. 1st, 2023

·         Revision Submission: Oct. 15th, 2023

·         Final Decision: Nov. 15th, 2023

Online Special Topic Publication: Dec. 1st, 2023

 

Submit your article through the JxCDC IEEE Author Portal:

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Discounts do not apply to undergraduate and graduate students. These discounts cannot be combined.

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Solid-State Circuits Sponsored Books

 

ISBN Copyright Year Author Title
9781119481515 2019 Baker CMOS: Circuit Design, Layout, and Simulation, all editions
9780470290262 2009 Baker CMOS: Mixed-Signal Circuit Design, all editions
9780471731726 2009 Strong Reliability Wearout Mechanisms
9780471709640 2008 Behzad Wireless LAN Radios: System Definition to Transistor Design
9780470184752 2008 Keeth DRAM Circuit Design: Fundamental and High-Speed Topics, all editions
9780471465850 2005 Schreier Understanding Delta-Sigma Data Converters
9780471447276 2003 Razavi Phase-Locking in High-Performance Systems: From Devices to Architectures
9780471227823 2002 Rutenbar Computer-Aided Design of Analog Integrated Circuits and Systems
9780780353985 2000 Ghosh Modeling and Asynchronous Distributed Simulation: Analyzing Complex Systems
9780780334793 2000 Hess Advanced Theory of Semiconductor Devices
9780780334595 1999 Abidi Integrated Circuits for Wireless Communications
9780780334472 1999 de Gyvez Integrated Circuit Manufacturability: The Art of Process and Design Integration
9780780347168 1999 Oklobdzija High-Performance System Design: Circuits and Logic
9780780334465 1999 Sanchez-Sinencio Low-Voltage/Low-Power Integrated Circuits and Systems: Low-Voltage Mixed-Signal Circuits
9780780334960 1999 Waynant Electronic and Photonic Circuits and Devices
9780780311732 1998 Brown
Nonvolatile Semiconductor Memory Technology: A Comprehensive Guide to Understanding and Using NVSM Devices
9780780310759 1998 Fernandez Symbolic Analysis Techniques: Applications to Analog Design Automation
9780780311749 1998 Sheu Multimedia Technology
9780780311497 1996 Razavi Monolithic Phase-Locked Loops and Clock Recovery Circuits : Theory and Design
9780780310933 1995 Razavi Principles of Data Conversion System Design
9780780310896 1995 Sherwani Routing in the Third Dimension : From VLSI Chips to MCMs
9780470088906 1994 Hecht, J.; Understanding Lasers: An Entry-Level Guide
9780879422851 1992 Candy Oversampling Delta-Sigma Data Converters : Theory, Design, and Simulation
9780879422462 1989 Gray Analog MOS Integrated Circuits, II

 

OJ-SSCS is now accepting submissions for the special issues below:

 


 

 

 

 Woog

Woogeun Rhee

OJ-SSCS Editor-in-Chief

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The IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS) is a fully open access journal that publishes papers in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as systems design, novel technologies, circuit modeling, and testing in areas of importance for integrated circuit design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Survey and tutorial papers in the area of solid-state circuits are publishable if similar content has not been published elsewhere. Including supportive hardware results is strongly encouraged.

The OJ-SSCS Editorial Board also wants to foster publications in novel areas of integrated circuits design. For this reason, we will propose regularly special sections on relevant and timely topics.

Our extensive review process and high-quality manuscript standards identical to the subscription-based IEEE Journal of Solid-State Circuits (JSSC) will allow authors to benefit from the 50 years of reputation build up by the Solid-State Circuits Society in integrated circuit design. Authors of open access papers published in the OJ-SSCS will obtain an equally-valid appreciation by their peers, and their research will be exposed to 5 million unique monthly users of the IEEE Xplore Digital Library without paywalls.


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The articles in this journal are peer reviewed in accordance with the requirements set forth in the IEEE PSPB Operations Manual (sections 8.2.1.C & 8.2.2.A). Each published article was reviewed by a minimum of two independent reviewers using a single-anonymous peer review process, where the identities of the reviewers are not known to the authors, but the reviewers know the identities of the authors. Articles will be screened for plagiarism before acceptance.

Corresponding authors from low-income countries are eligible for waived or reduced APCs.

 

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For papers submitted in 2024, the APC is US $1995 plus applicable local taxes. In 2024, 15 papers accepted for publication in the OJ-SSCS will be chosen by the Editor-in-Chief to receive a full waiver of the APC.

The following subsequent discounts apply:

  • IEEE Members receive a 5% discount.
  • IEEE Solid-State Circuits Society Members receive a 20% discount.

(5% and 20% discounts do not apply to undergraduate and graduate students. Discounts cannot be combined.) 

 

Discounts

IEEE Members receive a 5% discount.

IEEE Society Members receive a 20% discount.

These discounts cannot be combined.

For papers submitted in 2023, the Article Processing Charge (APC) is US$1950 plus applicable local taxes. The following discounts apply: IEEE Members receive a 5% discount. IEEE SSCS Members receive a 20% discount. Discounts do not apply to undergraduate and graduate students. These discounts cannot be combined. 

 

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Prior and related publications obviously refer to e.g. earlier conference papers on which the OJ-SSCS manuscript elaborates. But also other publications where (part of) the submitted work was disclosed, earlier work of you or your group in the same field on which the submitted manuscript builds further, etc. must be included.

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Submission Information

Detailed author information can be found here.

 

 

EDITOR-IN-CHIEF

Leonid Belostotski

University of Calgary

Calgary, AB, Canda

lbelosto@ieee.org 

 

ASSOCIATE EDITORS 

Tutorials Editor

Ali Sheikholeslami

University of Toronto

Toronto, Canada 

ali@eecg.utoronto.ca

 Associate Editor for the Far East

Hoi-Jun Yoo

Korea Advanaced Institute of Science and Technology

Daejeon, South Korea

hjyoo@kaist.ac.kr

Associate Editor for Europe and Africa

Harald Pretl

Johannes Kepler University

Liz, Australia

harald.pretl@jku.at 

Contributing Editor

Behzad Razavi

University of California

Los Angeles, California, USA

razavi@ee.ucla.edu

Contributing Editor

Chris Mangelsdorf

Analog Devices, retired 

San Diego, California 

chris.mangelsdorf@analog.com

News Editor

Danielle Marinese

IEEE

d.marinese@ieee.org

Associate Editor for Women in Circuits

Q. Jane Gu

University of California

Davis, CA

jgu@ucdavis.edu 

 

MAGAZINE ADVISORY BOARD

Chair: Rakesh Kumar, Technology Connexions (TCX), California, USA

 

Leonid Belostotski

University of Calgary

Calgary, AB, Canda

lbelosto@ieee.org 

Bill Bidermann

Bidermann Associates

San Diego, California, USA

bill@bidermann.com 

Payam Heydari

Chancellor's Professor

University of California, Irvine

payam@uci.edu

Erik Heijne

CERN, The European Organization for Nuclear Research

Geneva, Switzerland 

erik.heijne@cern.ch 

Hideto Hidaka, Fellow

Renesas Electronics Corp.

Tokyo, Japan 

hideto.hidaka.pz@renesas.com 

Richard Jaeger

Auburn University

Auburn, Alabama, USA

rj@jaegerengineering.com 

Tom Lee

Professor 

Stanford University

Stanford, California, USA

tomlee@ee.stanford.edu 

Jake Baker

Professor

Univeristy of Nevada

r.jacob.baker@unlv.edu

Ali Sheikholeslami

University of Toronto

Toronto, Canada 

ali@eecg.utoronto.ca 

Alice Wang

Everactive

Santa Clara, California, USA

aliwang@gmail.com 

Patrick Yue 

Hong Kong University of Science and Technology

Hong Kong, China 

eepatrick@ust.hk