Tiles

  • No Comments

A Runtime Reconfigurable Array (RTRA) for Multiprogram ML and DSP Acceleration With Hierarchical Partitioning and On-Chip Multilevel Scheduling

A Runtime Reconfigurable Array (RTRA) for Multiprogram ML and DSP Acceleration With Hierarchical Partitioning and On-Chip Multilevel Scheduling 150 150
Author(s): Hongseok Lee, Jack Burd, Tim Ling, Yao-Kai Yang, Nian-Shyang Chang, Wen-Ching Chen, Chi-Shi Chen, Tzi-Dar Chiueh, Michael Kuan-Tse Lee, Chia-Hsiang Yang, Dejan Marković

Abstract:

Emerging applications with highly dynamic digital signal processing (DSP) and machine-learning (ML) workloads demand a hardware platforms that simultaneously deliver high performance, high energy efficiency, and low-latency reconfiguration. Such systems must adapt to evolving algorithms, variable data rates, and multiprogram tenancy without incurring prohibitive switching overhead. The conventional reconfigurable architectures …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 5296 – 5312
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3715500
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Modeling/Rendering Unified 3DGS Processor Based on Locality-Optimized Computation and Reconfigurable Architecture

A Modeling/Rendering Unified 3DGS Processor Based on Locality-Optimized Computation and Reconfigurable Architecture 150 150
Author(s): Xiaoyu Feng, Hedi Wang, Songran Xiao, Huazhong Yang, Yongpan Liu

Abstract:

Traditional 3-D Gaussian-splatting (3DGS) modeling relies on iterative optimization, leading to substantial latency and limited generalizability. Feedforward 3DGS alleviates these limitations by generating Gaussians through a single network inference. However, most existing processors are optimized for optimization-based 3DGS and do not fully exploit the distinct computational characteristics of feedforward 3DGS. …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 14
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3737807
Publisher: IEEE

View on IEEE Xplore

  • No Comments

A Hybrid-Bonded 12.1 TOPS/mm2 56-Core DNN Processor With 2.5 Tb/s/mm2 3D Network on Chip in Intel 18A and Intel 3

A Hybrid-Bonded 12.1 TOPS/mm2 56-Core DNN Processor With 2.5 Tb/s/mm2 3D Network on Chip in Intel 18A and Intel 3 150 150
Author(s): Phil C. Knag, Gregory K. Chen, Shanshan Xie, Satish Yada, Wei Wu, Yu-Shiang Lin, Alexander Kashirin, Xiemei Meng, Russell Criss, Ana Sonia Leon, Carlos Tokunaga, Ram K. Krishnamurthy, James W. Tschanz

Abstract:

This article presents a modular 3D stacked manycore processor that integrates a general-purpose RISC-V base die with a domain-specific deep neural network (DNN) accelerator die using a 9 $\mu $ m hybrid-bonded interconnect (HBI). A custom $14 \times 4~\times 2$ 3D network-on-chip (3D NoC) provides a flat, distributed shared-memory address space across 112 tiles, enabling …

Published in: IEEE Journal of Solid-State Circuits
Page(s): 1 – 13
Year of Publication: 2026
Electronic ISSN: 1558-173X
DOI: 10.1109/JSSC.2026.3735250
Publisher: IEEE

View on IEEE Xplore

Search this website